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llvm::ARMTargetLowering Class Reference

#include <ARMISelLowering.h>

+ Inheritance diagram for llvm::ARMTargetLowering:

Public Types

enum  ConstraintType {
  C_Register, C_RegisterClass, C_Memory, C_Other,
  C_Unknown
}
 
enum  ConstraintWeight {
  CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2,
  CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better,
  CW_Constant = CW_Best, CW_Default = CW_Okay
}
 
typedef std::vector< ArgListEntryArgListTy
 
typedef std::vector
< AsmOperandInfo
AsmOperandInfoVector
 
enum  LegalizeAction { Legal, Promote, Expand, Custom }
 
enum  LegalizeTypeAction {
  TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat,
  TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector
}
 
enum  BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
 Enum that describes how the target represents true/false values. More...
 
enum  SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
 Enum that describes what type of support for selects the target has. More...
 
typedef std::pair
< LegalizeTypeAction, EVT
LegalizeKind
 

Public Member Functions

 ARMTargetLowering (TargetMachine &TM)
 
unsigned getJumpTableEncoding () const override
 
SDValue LowerOperation (SDValue Op, SelectionDAG &DAG) const override
 
void ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
 
const char * getTargetNodeName (unsigned Opcode) const override
 
bool isSelectSupported (SelectSupportKind Kind) const override
 
EVT getSetCCResultType (LLVMContext &Context, EVT VT) const override
 getSetCCResultType - Return the value type to use for ISD::SETCC. More...
 
MachineBasicBlockEmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB) const override
 
void AdjustInstrPostInstrSelection (MachineInstr *MI, SDNode *Node) const override
 
SDValue PerformCMOVCombine (SDNode *N, SelectionDAG &DAG) const
 PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. More...
 
SDValue PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override
 
bool isDesirableToTransformToIntegerOp (unsigned Opc, EVT VT) const override
 
bool allowsUnalignedMemoryAccesses (EVT VT, unsigned AddrSpace, bool *Fast) const override
 
EVT getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
 
bool isZExtFree (SDValue Val, EVT VT2) const override
 
bool allowTruncateForTailCall (Type *Ty1, Type *Ty2) const override
 
bool isLegalAddressingMode (const AddrMode &AM, Type *Ty) const override
 
bool isLegalT2ScaledAddressingMode (const AddrMode &AM, EVT VT) const
 
bool isLegalICmpImmediate (int64_t Imm) const override
 
bool isLegalAddImmediate (int64_t Imm) const override
 
bool getPreIndexedAddressParts (SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
 
bool getPostIndexedAddressParts (SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
 
void computeKnownBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const override
 
bool ExpandInlineAsm (CallInst *CI) const override
 
ConstraintType getConstraintType (const std::string &Constraint) const override
 
ConstraintWeight getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const override
 
std::pair< unsigned, const
TargetRegisterClass * > 
getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const override
 
void LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
 
const ARMSubtargetgetSubtarget () const
 
const TargetRegisterClassgetRegClassFor (MVT VT) const override
 
unsigned getMaximalGlobalOffset () const override
 
bool isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const override
 Returns true if a cast between SrcAS and DestAS is a noop. More...
 
FastISelcreateFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
 
Sched::Preference getSchedulingPreference (SDNode *N) const override
 
bool isShuffleMaskLegal (const SmallVectorImpl< int > &M, EVT VT) const override
 
bool isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const override
 
bool isFPImmLegal (const APFloat &Imm, EVT VT) const override
 
bool getTgtMemIntrinsic (IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
 
bool shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override
 Returns true if it is beneficial to convert a load of a constant to just the constant itself. More...
 
bool functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
 Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv. More...
 
ValueemitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
 
ValueemitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
 
bool shouldExpandAtomicInIR (Instruction *Inst) const override
 
virtual const MCExprLowerCustomJumpTableEntry (const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
 
virtual SDValue getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
 Returns relocation base for the given PIC jumptable. More...
 
virtual const MCExprgetPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
 
bool isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
 
void softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
 
std::pair< SDValue, SDValuemakeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
 Returns a pair of (return value, chain). More...
 
bool SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
 
virtual unsigned ComputeNumSignBitsForTargetNode (SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const
 
bool isConstTrueVal (const SDNode *N) const
 
bool isConstFalseVal (const SDNode *N) const
 
SDValue SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const
 
virtual bool isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
 
virtual bool isDesirableToCommuteWithShift (const SDNode *N) const
 Return true if it is profitable to move a following shift through this. More...
 
virtual bool isTypeDesirableForOp (unsigned, EVT VT) const
 
virtual bool IsDesirableToPromoteOp (SDValue, EVT &) const
 
std::pair< SDValue, SDValueLowerCallTo (CallLoweringInfo &CLI) const
 
virtual const char * getClearCacheBuiltinName () const
 
virtual MVT getTypeForExtArgOrReturn (MVT VT, ISD::NodeType) const
 
virtual const MCPhysReggetScratchRegisters (CallingConv::ID CC) const
 
virtual SDValue prepareVolatileOrAtomicLoad (SDValue Chain, SDLoc DL, SelectionDAG &DAG) const
 
virtual void LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
 
bool verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const
 
virtual AsmOperandInfoVector ParseConstraints (ImmutableCallSite CS) const
 
virtual ConstraintWeight getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const
 
virtual void ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
 
virtual const char * LowerXConstraint (EVT ConstraintVT) const
 
SDValue BuildExactSDIV (SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const
 Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant. More...
 
SDValue BuildSDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...
 
SDValue BuildUDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...
 
bool expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
 
bool expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
 
const TargetMachinegetTargetMachine () const
 
const DataLayoutgetDataLayout () const
 
const TargetLoweringObjectFilegetObjFileLowering () const
 
bool isBigEndian () const
 
bool isLittleEndian () const
 
virtual MVT getPointerTy (uint32_t=0) const
 
unsigned getPointerSizeInBits (uint32_t AS=0) const
 
unsigned getPointerTypeSizeInBits (Type *Ty) const
 
virtual MVT getScalarShiftAmountTy (EVT LHSTy) const
 
EVT getShiftAmountTy (EVT LHSTy) const
 
virtual MVT getVectorIdxTy () const
 
bool isSelectExpensive () const
 Return true if the select operation is expensive for this target. More...
 
bool hasMultipleConditionRegisters () const
 Return true if multiple condition registers are available. More...
 
bool hasExtractBitsInsn () const
 Return true if the target has BitExtract instructions. More...
 
virtual
TargetLoweringBase::LegalizeTypeAction 
getPreferredVectorAction (EVT VT) const
 Return the preferred vector type legalization action. More...
 
virtual bool shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const
 
bool isIntDivCheap () const
 
bool isSlowDivBypassed () const
 Returns true if target has indicated at least one type should be bypassed. More...
 
const DenseMap< unsigned int,
unsigned int > & 
getBypassSlowDivWidths () const
 
bool isPow2DivCheap () const
 Return true if pow2 div is cheaper than a chain of srl/add/sra. More...
 
bool isJumpExpensive () const
 
bool isPredictableSelectExpensive () const
 
virtual bool isLoadBitCastBeneficial (EVT, EVT) const
 
bool isMaskAndBranchFoldingLegal () const
 Return if the target supports combining a chain like: More...
 
virtual MVT::SimpleValueType getCmpLibcallReturnType () const
 
BooleanContent getBooleanContents (bool isVec, bool isFloat) const
 
BooleanContent getBooleanContents (EVT Type) const
 
Sched::Preference getSchedulingPreference () const
 Return target scheduling preference. More...
 
virtual const TargetRegisterClassgetRepRegClassFor (MVT VT) const
 
virtual uint8_t getRepRegClassCostFor (MVT VT) const
 
bool isTypeLegal (EVT VT) const
 
const ValueTypeActionImplgetValueTypeActions () const
 
LegalizeTypeAction getTypeAction (LLVMContext &Context, EVT VT) const
 
LegalizeTypeAction getTypeAction (MVT VT) const
 
EVT getTypeToTransformTo (LLVMContext &Context, EVT VT) const
 
EVT getTypeToExpandTo (LLVMContext &Context, EVT VT) const
 
unsigned getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 
virtual bool canOpTrap (unsigned Op, EVT VT) const
 
virtual bool isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const
 
LegalizeAction getOperationAction (unsigned Op, EVT VT) const
 
bool isOperationLegalOrCustom (unsigned Op, EVT VT) const
 
bool isOperationLegalOrPromote (unsigned Op, EVT VT) const
 
bool isOperationExpand (unsigned Op, EVT VT) const
 
bool isOperationLegal (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target. More...
 
LegalizeAction getLoadExtAction (unsigned ExtType, MVT VT) const
 
bool isLoadExtLegal (unsigned ExtType, EVT VT) const
 Return true if the specified load with extension is legal on this target. More...
 
LegalizeAction getTruncStoreAction (MVT ValVT, MVT MemVT) const
 
bool isTruncStoreLegal (EVT ValVT, EVT MemVT) const
 
LegalizeAction getIndexedLoadAction (unsigned IdxMode, MVT VT) const
 
bool isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getIndexedStoreAction (unsigned IdxMode, MVT VT) const
 
bool isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getCondCodeAction (ISD::CondCode CC, MVT VT) const
 
bool isCondCodeLegal (ISD::CondCode CC, MVT VT) const
 Return true if the specified condition code is legal on this target. More...
 
MVT getTypeToPromoteTo (unsigned Op, MVT VT) const
 
EVT getValueType (Type *Ty, bool AllowUnknown=false) const
 
MVT getSimpleValueType (Type *Ty, bool AllowUnknown=false) const
 Return the MVT corresponding to this LLVM type. See getValueType. More...
 
virtual unsigned getByValTypeAlignment (Type *Ty) const
 
MVT getRegisterType (MVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
MVT getRegisterType (LLVMContext &Context, EVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
unsigned getNumRegisters (LLVMContext &Context, EVT VT) const
 
virtual bool ShouldShrinkFPConstant (EVT) const
 
bool hasBigEndianPartOrdering (EVT VT) const
 
bool hasTargetDAGCombine (ISD::NodeType NT) const
 
unsigned getMaxStoresPerMemset (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memset. More...
 
unsigned getMaxStoresPerMemcpy (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memcpy. More...
 
unsigned getMaxStoresPerMemmove (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memmove. More...
 
virtual bool isSafeMemOpType (MVT) const
 
bool usesUnderscoreSetJmp () const
 Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...
 
bool usesUnderscoreLongJmp () const
 Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...
 
bool supportJumpTables () const
 Return whether the target can generate code for jump tables. More...
 
int getMinimumJumpTableEntries () const
 
unsigned getStackPointerRegisterToSaveRestore () const
 
unsigned getExceptionPointerRegister () const
 
unsigned getExceptionSelectorRegister () const
 
unsigned getJumpBufSize () const
 
unsigned getJumpBufAlignment () const
 
unsigned getMinStackArgumentAlignment () const
 Return the minimum stack alignment of an argument. More...
 
unsigned getMinFunctionAlignment () const
 Return the minimum function alignment. More...
 
unsigned getPrefFunctionAlignment () const
 Return the preferred function alignment. More...
 
unsigned getPrefLoopAlignment () const
 Return the preferred loop alignment. More...
 
bool getInsertFencesForAtomic () const
 
virtual bool getStackCookieLocation (unsigned &, unsigned &) const
 
Helpers for TargetTransformInfo implementations
int InstructionOpcodeToISD (unsigned Opcode) const
 Get the ISD node that corresponds to the Instruction class opcode. More...
 
std::pair< unsigned, MVTgetTypeLegalizationCost (Type *Ty) const
 Estimate the cost of type-legalization and the legalized type. More...
 

Static Public Member Functions

static ISD::NodeType getExtendForContent (BooleanContent Content)
 

Protected Member Functions

std::pair< const
TargetRegisterClass *, uint8_t > 
findRepresentativeClass (MVT VT) const override
 
void initActions ()
 Initialize all of the actions to default values. More...
 

Private Types

typedef SmallVector< std::pair
< unsigned, SDValue >, 8 > 
RegsToPassVector
 

Private Member Functions

void addTypeForNEON (MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT)
 
void addDRTypeForNEON (MVT VT)
 
void addQRTypeForNEON (MVT VT)
 
std::pair< SDValue, SDValuegetARMXALUOOp (SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const
 
void PassF64ArgInRegs (SDLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl< SDValue > &MemOpChains, ISD::ArgFlagsTy Flags) const
 
SDValue GetF64FormalArgument (CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, SDLoc dl) const
 
CallingConv::ID getEffectiveCallingConv (CallingConv::ID CC, bool isVarArg) const
 
CCAssignFnCCAssignFnForNode (CallingConv::ID CC, bool Return, bool isVarArg) const
 
SDValue LowerMemOpCallTo (SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
 LowerMemOpCallTo - Store the argument to the stack. More...
 
SDValue LowerEH_SJLJ_SETJMP (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerEH_SJLJ_LONGJMP (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerINTRINSIC_WO_CHAIN (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const
 
SDValue LowerBlockAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerGlobalAddressDarwin (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerGlobalAddressELF (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerGlobalAddressWindows (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerGlobalTLSAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerToTLSGeneralDynamicModel (GlobalAddressSDNode *GA, SelectionDAG &DAG) const
 
SDValue LowerToTLSExecModels (GlobalAddressSDNode *GA, SelectionDAG &DAG, TLSModel::Model model) const
 
SDValue LowerGLOBAL_OFFSET_TABLE (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerBR_JT (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerXALUO (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSELECT (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSELECT_CC (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerBR_CC (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFCOPYSIGN (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerRETURNADDR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFRAMEADDR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerShiftRightParts (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerShiftLeftParts (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFLT_ROUNDS_ (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerConstantFP (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const
 
SDValue LowerBUILD_VECTOR (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const
 
SDValue LowerFSINCOS (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerDivRem (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerDYNAMIC_STACKALLOC (SDValue Op, SelectionDAG &DAG) const
 
unsigned getRegisterByName (const char *RegName, EVT VT) const override
 
bool isFMAFasterThanFMulAndFAdd (EVT VT) const override
 
SDValue ReconstructShuffle (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerCallResult (SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
 
SDValue LowerFormalArguments (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
 
int StoreByValRegs (CCState &CCInfo, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, const Value *OrigArg, unsigned InRegsParamRecordIdx, unsigned OffsetFromOrigArg, unsigned ArgOffset, unsigned ArgSize, bool ForceMutable, unsigned ByValStoreOffset, unsigned TotalArgRegsSaveSize) const
 
void VarArgStyleRegisters (CCState &CCInfo, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, unsigned ArgOffset, unsigned TotalArgRegsSaveSize, bool ForceMutable=false) const
 
void computeRegArea (CCState &CCInfo, MachineFunction &MF, unsigned InRegsParamRecordIdx, unsigned ArgSize, unsigned &ArgRegsSize, unsigned &ArgRegsSaveSize) const
 
SDValue LowerCall (TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
 
void HandleByVal (CCState *, unsigned &, unsigned) const override
 HandleByVal - Target-specific cleanup for ByVal support. More...
 
bool IsEligibleForTailCallOptimization (SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
 
bool CanLowerReturn (CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
 
SDValue LowerReturn (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc dl, SelectionDAG &DAG) const override
 
bool isUsedByReturnOnly (SDNode *N, SDValue &Chain) const override
 
bool mayBeEmittedAsTailCall (CallInst *CI) const override
 
SDValue getARMCmp (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const
 
SDValue getVFPCmp (SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl) const
 Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. More...
 
SDValue duplicateCmp (SDValue Cmp, SelectionDAG &DAG) const
 
SDValue OptimizeVFPBrcond (SDValue Op, SelectionDAG &DAG) const
 
void SetupEntryBlockForSjLj (MachineInstr *MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI) const
 
MachineBasicBlockEmitSjLjDispatchBlock (MachineInstr *MI, MachineBasicBlock *MBB) const
 
bool RemapAddSubWithFlags (MachineInstr *MI, MachineBasicBlock *BB) const
 
MachineBasicBlockEmitStructByval (MachineInstr *MI, MachineBasicBlock *MBB) const
 
MachineBasicBlockEmitLowered__chkstk (MachineInstr *MI, MachineBasicBlock *MBB) const
 

Private Attributes

const ARMSubtargetSubtarget
 
const TargetRegisterInfoRegInfo
 
const InstrItineraryDataItins
 
unsigned ARMPCLabelIndex
 

Helpers for load-linked/store-conditional atomic expansion.

virtual void resetOperationActions ()
 Reset the operation actions based on target options. More...
 
virtual bool GetAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const
 
virtual int getScalingFactorCost (const AddrMode &AM, Type *Ty) const
 Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...
 
virtual bool isVectorShiftByScalarCheap (Type *Ty) const
 
virtual bool isTruncateFree (Type *, Type *) const
 
virtual bool isTruncateFree (EVT, EVT) const
 Reset the operation actions based on target options. More...
 
virtual bool isZExtFree (Type *, Type *) const
 
virtual bool isZExtFree (EVT, EVT) const
 Reset the operation actions based on target options. More...
 
virtual bool hasPairedLoad (Type *, unsigned &) const
 
virtual bool hasPairedLoad (EVT, unsigned &) const
 Specify maximum number of store instructions per memset call. More...
 
virtual bool isFNegFree (EVT VT) const
 
virtual bool isFAbsFree (EVT VT) const
 
virtual bool isNarrowingProfitable (EVT, EVT) const
 
void setLibcallName (RTLIB::Libcall Call, const char *Name)
 Rename the default libcall routine name for the specified libcall. More...
 
const char * getLibcallName (RTLIB::Libcall Call) const
 Get the libcall routine name for the specified libcall. More...
 
void setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
 
ISD::CondCode getCmpLibcallCC (RTLIB::Libcall Call) const
 
void setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
 Set the CallingConv that should be used for the specified libcall. More...
 
CallingConv::ID getLibcallCallingConv (RTLIB::Libcall Call) const
 Get the CallingConv that should be used for the specified libcall. More...
 
LegalizeKind getTypeConversion (LLVMContext &Context, EVT VT) const
 Reset the operation actions based on target options. More...
 
void setBooleanContents (BooleanContent Ty)
 
void setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
 
void setBooleanVectorContents (BooleanContent Ty)
 
void setSchedulingPreference (Sched::Preference Pref)
 Specify the target scheduling preference. More...
 
void setUseUnderscoreSetJmp (bool Val)
 
void setUseUnderscoreLongJmp (bool Val)
 
void setSupportJumpTables (bool Val)
 Indicate whether the target can generate code for jump tables. More...
 
void setMinimumJumpTableEntries (int Val)
 
void setStackPointerRegisterToSaveRestore (unsigned R)
 
void setExceptionPointerRegister (unsigned R)
 
void setExceptionSelectorRegister (unsigned R)
 
void setSelectIsExpensive (bool isExpensive=true)
 
void setHasMultipleConditionRegisters (bool hasManyRegs=true)
 
void setHasExtractBitsInsn (bool hasExtractInsn=true)
 
void setJumpIsExpensive (bool isExpensive=true)
 
void setIntDivIsCheap (bool isCheap=true)
 
void addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
 Tells the code generator which bitwidths to bypass. More...
 
void setPow2DivIsCheap (bool isCheap=true)
 
void addRegisterClass (MVT VT, const TargetRegisterClass *RC)
 
void clearRegisterClasses ()
 Remove all register classes. More...
 
void clearOperationActions ()
 Remove all operation actions. More...
 
void computeRegisterProperties ()
 
void setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
 
void setLoadExtAction (unsigned ExtType, MVT VT, LegalizeAction Action)
 
void setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
 
void setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 
void setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 
void setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
 
void AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 
void setTargetDAGCombine (ISD::NodeType NT)
 
void setJumpBufSize (unsigned Size)
 Set the target's required jmp_buf buffer size (in bytes); default is 200. More...
 
void setJumpBufAlignment (unsigned Align)
 
void setMinFunctionAlignment (unsigned Align)
 Set the target's minimum function alignment (in log2(bytes)) More...
 
void setPrefFunctionAlignment (unsigned Align)
 
void setPrefLoopAlignment (unsigned Align)
 
void setMinStackArgumentAlignment (unsigned Align)
 Set the minimum stack alignment of an argument (in log2(bytes)). More...
 
void setInsertFencesForAtomic (bool fence)
 
bool isLegalRC (const TargetRegisterClass *RC) const
 
MachineBasicBlockemitPatchPoint (MachineInstr *MI, MachineBasicBlock *MBB) const
 
unsigned MaxStoresPerMemset
 Specify maximum number of store instructions per memset call. More...
 
unsigned MaxStoresPerMemsetOptSize
 
unsigned MaxStoresPerMemcpy
 Specify maximum bytes of store instructions per memcpy call. More...
 
unsigned MaxStoresPerMemcpyOptSize
 
unsigned MaxStoresPerMemmove
 Specify maximum bytes of store instructions per memmove call. More...
 
unsigned MaxStoresPerMemmoveOptSize
 
bool PredictableSelectIsExpensive
 
bool MaskAndBranchFoldingIsLegal
 

Detailed Description

Definition at line 233 of file ARMISelLowering.h.

Member Typedef Documentation

typedef std::vector<ArgListEntry> llvm::TargetLowering::ArgListTy
inherited

Definition at line 2126 of file TargetLowering.h.

Definition at line 2484 of file TargetLowering.h.

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

Definition at line 106 of file TargetLowering.h.

typedef SmallVector<std::pair<unsigned, SDValue>, 8> llvm::ARMTargetLowering::RegsToPassVector
private

Definition at line 423 of file ARMISelLowering.h.

Member Enumeration Documentation

Enum that describes how the target represents true/false values.

Enumerator
UndefinedBooleanContent 
ZeroOrOneBooleanContent 
ZeroOrNegativeOneBooleanContent 

Definition at line 109 of file TargetLowering.h.

Enumerator
C_Register 
C_RegisterClass 
C_Memory 
C_Other 
C_Unknown 

Definition at line 2425 of file TargetLowering.h.

2425  {
2426  C_Register, // Constraint represents specific register(s).
2427  C_RegisterClass, // Constraint represents any of register(s) in class.
2428  C_Memory, // Memory constraint.
2429  C_Other, // Something else.
2430  C_Unknown // Unsupported constraint.
2431  };
Enumerator
CW_Invalid 
CW_Okay 
CW_Good 
CW_Better 
CW_Best 
CW_SpecificReg 
CW_Register 
CW_Memory 
CW_Constant 
CW_Default 

Definition at line 2433 of file TargetLowering.h.

2433  {
2434  // Generic weights.
2435  CW_Invalid = -1, // No match.
2436  CW_Okay = 0, // Acceptable.
2437  CW_Good = 1, // Good weight.
2438  CW_Better = 2, // Better weight.
2439  CW_Best = 3, // Best weight.
2440 
2441  // Well-known weights.
2442  CW_SpecificReg = CW_Okay, // Specific register operands.
2443  CW_Register = CW_Good, // Register operands.
2444  CW_Memory = CW_Better, // Memory operands.
2445  CW_Constant = CW_Best, // Constant operand.
2446  CW_Default = CW_Okay // Default or don't know type.
2447  };

This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.

Enumerator
Legal 
Promote 
Expand 
Custom 

Definition at line 84 of file TargetLowering.h.

84  {
85  Legal, // The target natively supports this operation.
86  Promote, // This operation should be executed in a larger type.
87  Expand, // Try to expand this to other ops, otherwise use a libcall.
88  Custom // Use the LowerOperation hook to implement custom lowering.
89  };

This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.

Enumerator
TypeLegal 
TypePromoteInteger 
TypeExpandInteger 
TypeSoftenFloat 
TypeExpandFloat 
TypeScalarizeVector 
TypeSplitVector 
TypeWidenVector 

Definition at line 93 of file TargetLowering.h.

93  {
94  TypeLegal, // The target natively supports this type.
95  TypePromoteInteger, // Replace this integer with a larger one.
96  TypeExpandInteger, // Split this integer into two of half the size.
97  TypeSoftenFloat, // Convert this float to a same size integer type.
98  TypeExpandFloat, // Split this float into two of half the size.
99  TypeScalarizeVector, // Replace this one-element vector with its element.
100  TypeSplitVector, // Split this vector into two of half the size.
101  TypeWidenVector // This vector should be widened into a larger vector.
102  };

Enum that describes what type of support for selects the target has.

Enumerator
ScalarValSelect 
ScalarCondVectorVal 
VectorMaskSelect 

Definition at line 116 of file TargetLowering.h.

116  {
117  ScalarValSelect, // The target supports scalar selects (ex: cmov).
118  ScalarCondVectorVal, // The target supports selects with a scalar condition
119  // and vector values (ex: cmov).
120  VectorMaskSelect // The target supports vector selects with a vector
121  // mask (ex: x86 blends).
122  };

Constructor & Destructor Documentation

ARMTargetLowering::ARMTargetLowering ( TargetMachine TM)
explicit

Definition at line 166 of file ARMISelLowering.cpp.

169  RegInfo = TM.getRegisterInfo();
171 
173 
174  if (Subtarget->isTargetMachO()) {
175  // Uses VFP for Thumb libfuncs if available.
176  if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
178  // Single-precision floating-point arithmetic.
179  setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
180  setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
181  setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
182  setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
183 
184  // Double-precision floating-point arithmetic.
185  setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
186  setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
187  setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
188  setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
189 
190  // Single-precision comparisons.
191  setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
192  setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
193  setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
194  setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
195  setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
196  setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
197  setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
198  setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
199 
208 
209  // Double-precision comparisons.
210  setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
211  setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
212  setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
213  setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
214  setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
215  setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
216  setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
217  setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
218 
227 
228  // Floating-point to integer conversions.
229  // i64 conversions are done via library routines even when generating VFP
230  // instructions, so use the same ones.
231  setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
232  setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
233  setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
234  setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
235 
236  // Conversions between floating types.
237  setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
238  setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
239 
240  // Integer to floating-point conversions.
241  // i64 conversions are done via library routines even when generating VFP
242  // instructions, so use the same ones.
243  // FIXME: There appears to be some naming inconsistency in ARM libgcc:
244  // e.g., __floatunsidf vs. __floatunssidfvfp.
245  setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
246  setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
247  setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
248  setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
249  }
250  }
251 
252  // These libcalls are not available in 32-bit.
256 
259  static const struct {
260  const RTLIB::Libcall Op;
261  const char * const Name;
262  const CallingConv::ID CC;
263  const ISD::CondCode Cond;
264  } LibraryCalls[] = {
265  // Double-precision floating-point arithmetic helper functions
266  // RTABI chapter 4.1.2, Table 2
271 
272  // Double-precision floating-point comparison helper functions
273  // RTABI chapter 4.1.2, Table 3
274  { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
275  { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
276  { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
277  { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
278  { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
279  { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
280  { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
281  { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
282 
283  // Single-precision floating-point arithmetic helper functions
284  // RTABI chapter 4.1.2, Table 4
289 
290  // Single-precision floating-point comparison helper functions
291  // RTABI chapter 4.1.2, Table 5
292  { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
293  { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
294  { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
295  { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
296  { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
297  { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
298  { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
299  { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
300 
301  // Floating-point to integer conversions.
302  // RTABI chapter 4.1.2, Table 6
311 
312  // Conversions between floating types.
313  // RTABI chapter 4.1.2, Table 7
316 
317  // Integer to floating-point conversions.
318  // RTABI chapter 4.1.2, Table 8
327 
328  // Long long helper functions
329  // RTABI chapter 4.2, Table 9
334 
335  // Integer division functions
336  // RTABI chapter 4.3.1
345 
346  // Memory operations
347  // RTABI chapter 4.3.4
351  };
352 
353  for (const auto &LC : LibraryCalls) {
354  setLibcallName(LC.Op, LC.Name);
355  setLibcallCallingConv(LC.Op, LC.CC);
356  if (LC.Cond != ISD::SETCC_INVALID)
357  setCmpLibcallCC(LC.Op, LC.Cond);
358  }
359  }
360 
361  if (Subtarget->isTargetWindows()) {
362  static const struct {
363  const RTLIB::Libcall Op;
364  const char * const Name;
365  const CallingConv::ID CC;
366  } LibraryCalls[] = {
375  };
376 
377  for (const auto &LC : LibraryCalls) {
378  setLibcallName(LC.Op, LC.Name);
379  setLibcallCallingConv(LC.Op, LC.CC);
380  }
381  }
382 
383  // Use divmod compiler-rt calls for iOS 5.0 and later.
384  if (Subtarget->getTargetTriple().isiOS() &&
386  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
387  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
388  }
389 
390  if (Subtarget->isThumb1Only())
391  addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
392  else
393  addRegisterClass(MVT::i32, &ARM::GPRRegClass);
394  if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
395  !Subtarget->isThumb1Only()) {
396  addRegisterClass(MVT::f32, &ARM::SPRRegClass);
397  if (!Subtarget->isFPOnlySP())
398  addRegisterClass(MVT::f64, &ARM::DPRRegClass);
399  }
400 
401  for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
402  VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
403  for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404  InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
406  (MVT::SimpleValueType)InnerVT, Expand);
410 
415 
417  }
418 
421 
422  if (Subtarget->hasNEON()) {
428 
435 
436  // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
437  // neither Neon nor VFP support any arithmetic operations on it.
438  // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
439  // supported for v4f32.
443  // FIXME: Code duplication: FDIV and FREM are expanded always, see
444  // ARMTargetLowering::addTypeForNEON method for details.
447  // FIXME: Create unittest.
448  // In another words, find a way when "copysign" appears in DAG with vector
449  // operands.
451  // FIXME: Code duplication: SETCC has custom operation action, see
452  // ARMTargetLowering::addTypeForNEON method for details.
454  // FIXME: Create unittest for FNEG and for FABS.
467  // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
474 
490 
491  // Mark v2f32 intrinsics.
507 
508  // Neon does not support some operations on v1i64 and v2i64 types.
510  // Custom handling for some quad-vector types to detect VMULL.
514  // Custom handling for some vector types to avoid expensive expansions
521  // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
522  // a destination type that is wider than the source, and nor does
523  // it have a FP_TO_[SU]INT instruction with a narrower destination than
524  // source.
529 
532 
533  // NEON does not have single instruction CTPOP for vectors with element
534  // types wider than 8-bits. However, custom lowering can leverage the
535  // v8i8/v16i8 vcnt instruction.
540 
541  // NEON only has FMA instructions as of VFP4.
542  if (!Subtarget->hasVFP4()) {
545  }
546 
564 
565  // It is legal to extload from v4i8 to v4i16 or v4i32.
566  MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
568  MVT::v2i32};
569  for (unsigned i = 0; i < 6; ++i) {
573  }
574  }
575 
576  // ARM and Thumb2 support UMLAL/SMLAL.
577  if (!Subtarget->isThumb1Only())
579 
580 
582 
583  // ARM does not have floating-point extending loads.
586 
587  // ... or truncating stores
591 
592  // ARM does not have i1 sign extending load.
594 
595  // ARM supports all 4 flavors of integer indexed load / store.
596  if (!Subtarget->isThumb1Only()) {
597  for (unsigned im = (unsigned)ISD::PRE_INC;
598  im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
607  }
608  }
609 
614 
615  // i64 operation support.
618  if (Subtarget->isThumb1Only()) {
621  }
623  || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
625 
631 
632  if (!Subtarget->isThumb1Only()) {
633  // FIXME: We should do this for Thumb1 as well.
638  }
639 
640  // ARM does not have ROTL.
646 
647  // These just redirect to CTTZ and CTLZ on ARM.
650 
652 
653  // Only ARMv6 has BSWAP.
654  if (!Subtarget->hasV6Ops())
656 
657  if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
659  // These are expanded into libcalls if the cpu doesn't have HW divider.
662  }
663 
664  // FIXME: Also set divmod for SREM on EABI
667  // Register based DivRem for AEABI (RTABI 4.2)
668  if (Subtarget->isTargetAEABI()) {
669  setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
670  setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
671  setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
672  setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
673  setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
674  setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
675  setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
676  setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
677 
686 
689  } else {
692  }
693 
699 
701 
702  // Use the default implementation.
709 
710  if (!Subtarget->isTargetMachO()) {
711  // Non-MachO platforms may return values in these registers via the
712  // personality function.
715  }
716 
719  else
721 
722  // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
723  // the default expansion.
725  // ATOMIC_FENCE needs custom lowering; the others should have been expanded
726  // to ldrex/strex loops already.
728 
729  // On v8, we have particularly efficient implementations of atomic fences
730  // if they can be combined with nearby atomic loads and stores.
731  if (!Subtarget->hasV8Ops()) {
732  // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
734  }
735  } else {
736  // If there's anything we can use as a barrier, go through custom lowering
737  // for ATOMIC_FENCE.
740 
741  // Set them all for expansion, which will force libcalls.
754  // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
755  // Unordered/Monotonic case.
758  }
759 
761 
762  // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
763  if (!Subtarget->hasV6Ops()) {
766  }
768 
769  if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
770  !Subtarget->isThumb1Only()) {
771  // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
772  // iff target supports vfp2.
775  }
776 
777  // We want to custom lower some of our intrinsics.
779  if (Subtarget->isTargetDarwin()) {
782  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
783  }
784 
794 
800 
801  // We don't support sin/cos/fmod/copysign/pow
810  if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
811  !Subtarget->isThumb1Only()) {
814  }
817 
818  if (!Subtarget->hasVFP4()) {
821  }
822 
823  // Various VFP goodness
824  if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
825  // int <-> fp are custom expanded into bit_convert + ARMISD ops.
826  if (Subtarget->hasVFP2()) {
831  }
832 
833  // v8 adds f64 <-> f16 conversion. Before that it should be expanded.
834  if (!Subtarget->hasV8Ops()) {
837  }
838 
839  // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
840  if (!Subtarget->hasFP16()) {
843  }
844  }
845 
846  // Combine sin / cos into one node or libcall if possible.
847  if (Subtarget->hasSinCos()) {
848  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
851  // For iOS, we don't want to the normal expansion of a libcall to
852  // sincos. We want to issue a libcall to __sincos_stret.
855  }
856  }
857 
858  // We have target-specific dag combine patterns for the following nodes:
859  // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
866 
867  if (Subtarget->hasV6Ops())
869 
871 
873  !Subtarget->hasVFP2())
875  else
877 
878  //// temporary - rewrite interface to use type
879  MaxStoresPerMemset = 8;
881  MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
883  MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
885 
886  // On ARM arguments smaller than 4 bytes are extended, so all arguments
887  // are at least 4 bytes aligned.
889 
890  // Prefer likely predicted branches to selects on out-of-order cores.
892 
894 }
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:222
bool isFPOnlySP() const
Definition: ARMSubtarget.h:329
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:93
void setBooleanVectorContents(BooleanContent Ty)
bool hasV6Ops() const
Definition: ARMSubtarget.h:288
Same for subtraction.
Definition: ISDOpcodes.h:221
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
bool hasDivide() const
Definition: ARMSubtarget.h:318
The address of the GOT.
Definition: ISDOpcodes.h:66
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
bool isTargetAEABI() const
Definition: ARMSubtarget.h:364
bool hasV8Ops() const
Definition: ARMSubtarget.h:292
bool isTargetDarwin() const
Definition: ARMSubtarget.h:346
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
const InstrItineraryData * Itins
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
virtual const InstrItineraryData * getInstrItineraryData() const
bool isThumb() const
Definition: ARMSubtarget.h:400
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:344
static TargetLoweringObjectFile * createTLOF(const Triple &TT)
bool isTargetMachO() const
Definition: ARMSubtarget.h:355
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
bool hasNEON() const
Definition: ARMSubtarget.h:311
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:322
bool hasVFP4() const
Definition: ARMSubtarget.h:309
bool hasARMOps() const
Definition: ARMSubtarget.h:305
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:355
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
void setTargetDAGCombine(ISD::NodeType NT)
const TargetRegisterInfo * RegInfo
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:622
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:317
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
bool hasSinCos() const
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
void setLoadExtAction(unsigned ExtType, MVT VT, LegalizeAction Action)
TargetLowering(const TargetLowering &) LLVM_DELETED_FUNCTION
const STC & getSubtarget() const
void setExceptionPointerRegister(unsigned R)
const ARMSubtarget * Subtarget
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:314
bool hasVFP2() const
Definition: ARMSubtarget.h:307
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
void setExceptionSelectorRegister(unsigned R)
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
const StringRef getTargetTriple() const
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
Definition: Triple.h:317
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
bool isThumb2() const
Definition: ARMSubtarget.h:402
bool hasV5TOps() const
Definition: ARMSubtarget.h:286
void setStackPointerRegisterToSaveRestore(unsigned R)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
virtual const TargetRegisterInfo * getRegisterInfo() const
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:490
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool isLikeA9() const
Definition: ARMSubtarget.h:301
void setMinStackArgumentAlignment(unsigned Align)
Set the minimum stack alignment of an argument (in log2(bytes)).
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
void setInsertFencesForAtomic(bool fence)
bool hasFP16() const
Definition: ARMSubtarget.h:341
bool isWindowsItaniumEnvironment() const
Test whether the architecture is 64-bit.
Definition: Triple.h:378
bool isAAPCS_ABI() const
Definition: ARMSubtarget.h:395
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:319
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
bool hasThumb2DSP() const
Definition: ARMSubtarget.h:338
bool isTargetWindows() const
Definition: ARMSubtarget.h:351
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)

Member Function Documentation

void llvm::TargetLoweringBase::addBypassSlowDiv ( unsigned int  SlowBitWidth,
unsigned int  FastBitWidth 
)
inlineprotectedinherited

Tells the code generator which bitwidths to bypass.

Definition at line 1063 of file TargetLowering.h.

1063  {
1064  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1065  }
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
void ARMTargetLowering::addDRTypeForNEON ( MVT  VT)
private

Definition at line 148 of file ARMISelLowering.cpp.

148  {
149  addRegisterClass(VT, &ARM::DPRRegClass);
151 }
void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT)
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
void llvm::TargetLoweringBase::AddPromotedToType ( unsigned  Opc,
MVT  OrigVT,
MVT  DestVT 
)
inlineprotectedinherited

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. If that default is insufficient, this method can be used by the target to override the default.

Definition at line 1173 of file TargetLowering.h.

1173  {
1174  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1175  }
std::map< std::pair< unsigned, MVT::SimpleValueType >, MVT::SimpleValueType > PromoteToType
void ARMTargetLowering::addQRTypeForNEON ( MVT  VT)
private

Definition at line 153 of file ARMISelLowering.cpp.

153  {
154  addRegisterClass(VT, &ARM::DPairRegClass);
156 }
void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT)
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
void llvm::TargetLoweringBase::addRegisterClass ( MVT  VT,
const TargetRegisterClass RC 
)
inlineprotectedinherited

Add the specified register class as an available regclass for the specified value type. This indicates the selector can handle values of that class natively.

Definition at line 1074 of file TargetLowering.h.

1074  {
1075  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1076  AvailableRegClasses.push_back(std::make_pair(VT, RC));
1077  RegClassForVT[VT.SimpleTy] = RC;
1078  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
std::vector< std::pair< MVT, const TargetRegisterClass * > > AvailableRegClasses
True if this is a little endian target.
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
void ARMTargetLowering::addTypeForNEON ( MVT  VT,
MVT  PromotedLdStVT,
MVT  PromotedBitwiseVT 
)
private

Definition at line 89 of file ARMISelLowering.cpp.

90  {
91  if (VT != PromotedLdStVT) {
93  AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
94 
96  AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
97  }
98 
99  MVT ElemTy = VT.getVectorElementType();
100  if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
104  if (ElemTy == MVT::i32) {
109  } else {
114  }
123  if (VT.isInteger()) {
127  }
128 
129  // Promote all bit-wise operations.
130  if (VT.isInteger() && VT != PromotedBitwiseVT) {
132  AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
134  AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
136  AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
137  }
138 
139  // Neon does not support vector divide/remainder operations.
146 }
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
MVT getVectorElementType() const
void ARMTargetLowering::AdjustInstrPostInstrSelection ( MachineInstr MI,
SDNode Node 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 7490 of file ARMISelLowering.cpp.

7491  {
7492  if (!MI->hasPostISelHook()) {
7494  "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
7495  return;
7496  }
7497 
7498  const MCInstrDesc *MCID = &MI->getDesc();
7499  // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7500  // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7501  // operand is still set to noreg. If needed, set the optional operand's
7502  // register to CPSR, and remove the redundant implicit def.
7503  //
7504  // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7505 
7506  // Rename pseudo opcodes.
7507  unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7508  if (NewOpc) {
7509  const ARMBaseInstrInfo *TII =
7510  static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
7511  MCID = &TII->get(NewOpc);
7512 
7513  assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7514  "converted opcode should be the same except for cc_out");
7515 
7516  MI->setDesc(*MCID);
7517 
7518  // Add the optional cc_out operand
7519  MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7520  }
7521  unsigned ccOutIdx = MCID->getNumOperands() - 1;
7522 
7523  // Any ARM instruction that sets the 's' bit should specify an optional
7524  // "cc_out" operand in the last operand position.
7525  if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7526  assert(!NewOpc && "Optional cc_out operand required");
7527  return;
7528  }
7529  // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7530  // since we already have an optional CPSR def.
7531  bool definesCPSR = false;
7532  bool deadCPSR = false;
7533  for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7534  i != e; ++i) {
7535  const MachineOperand &MO = MI->getOperand(i);
7536  if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7537  definesCPSR = true;
7538  if (MO.isDead())
7539  deadCPSR = true;
7540  MI->RemoveOperand(i);
7541  break;
7542  }
7543  }
7544  if (!definesCPSR) {
7545  assert(!NewOpc && "Optional cc_out operand required");
7546  return;
7547  }
7548  assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
7549  if (deadCPSR) {
7550  assert(!MI->getOperand(ccOutIdx).getReg() &&
7551  "expect uninitialized optional cc_out operand");
7552  return;
7553  }
7554 
7555  // If this instruction was defined with an optional CPSR def and its dag node
7556  // had a live implicit CPSR def, then activate the optional CPSR def.
7557  MachineOperand &MO = MI->getOperand(ccOutIdx);
7558  MO.setReg(ARM::CPSR);
7559  MO.setIsDef(true);
7560 }
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Definition: MachineInstr.h:595
const TargetMachine & getTargetMachine() const
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
bool isDead() const
const MCInstrDesc & getDesc() const
Definition: MachineInstr.h:266
const HexagonInstrInfo * TII
static bool definesCPSR(MachineInstr *MI)
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
unsigned getNumOperands() const
Definition: MachineInstr.h:274
void RemoveOperand(unsigned i)
int getOpcode() const
Definition: MachineInstr.h:270
assert(Globals.size() > 1)
bool isOptionalDef() const
Definition: MCInstrDesc.h:87
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
virtual const TargetInstrInfo * getInstrInfo() const
void setDesc(const MCInstrDesc &tid)
void addOperand(MachineFunction &MF, const MachineOperand &Op)
bool hasAnyUseOfValue(unsigned Value) const
void setReg(unsigned Reg)
unsigned getReg() const
getReg - Returns the register number.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction. Note that variadic (isVari...
Definition: MCInstrDesc.h:190
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:148
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Definition: MachineInstr.h:389
bool ARMTargetLowering::allowsUnalignedMemoryAccesses ( EVT  VT,
unsigned  AddrSpace,
bool *  Fast 
) const
overridevirtual

allowsUnalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the specified type. Returns whether it is "fast" by reference in the second argument.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9699 of file ARMISelLowering.cpp.

9700  {
9701  // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
9702  bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
9703 
9704  switch (VT.getSimpleVT().SimpleTy) {
9705  default:
9706  return false;
9707  case MVT::i8:
9708  case MVT::i16:
9709  case MVT::i32: {
9710  // Unaligned access can use (for example) LRDB, LRDH, LDR
9711  if (AllowsUnaligned) {
9712  if (Fast)
9713  *Fast = Subtarget->hasV7Ops();
9714  return true;
9715  }
9716  return false;
9717  }
9718  case MVT::f64:
9719  case MVT::v2f64: {
9720  // For any little-endian targets with neon, we can support unaligned ld/st
9721  // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
9722  // A big-endian target may also explicitly support unaligned accesses
9723  if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
9724  if (Fast)
9725  *Fast = true;
9726  return true;
9727  }
9728  return false;
9729  }
9730  }
9731 }
bool isLittleEndian() const
SimpleValueType SimpleTy
bool hasV7Ops() const
Definition: ARMSubtarget.h:291
bool hasNEON() const
Definition: ARMSubtarget.h:311
const ARMSubtarget * Subtarget
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:414
MVT getSimpleVT() const
Definition: ValueTypes.h:204
bool ARMTargetLowering::allowTruncateForTailCall ( Type Ty1,
Type Ty2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9794 of file ARMISelLowering.cpp.

9794  {
9795  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9796  return false;
9797 
9798  if (!isTypeLegal(EVT::getEVT(Ty1)))
9799  return false;
9800 
9801  assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
9802 
9803  // Assuming the caller doesn't have a zeroext or signext return parameter,
9804  // truncation all the way down to i1 is valid.
9805  return true;
9806 }
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
bool isIntegerTy() const
Definition: Type.h:193
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:275
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
SDValue TargetLowering::BuildExactSDIV ( SDValue  Op1,
SDValue  Op2,
SDLoc  dl,
SelectionDAG DAG 
) const
inherited

Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant.

Definition at line 2617 of file TargetLowering.cpp.

2618  {
2619  ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2620  APInt d = C->getAPIntValue();
2621  assert(d != 0 && "Division by zero!");
2622 
2623  // Shift the value upfront if it is even, so the LSB is one.
2624  unsigned ShAmt = d.countTrailingZeros();
2625  if (ShAmt) {
2626  // TODO: For UDIV use SRL instead of SRA.
2627  SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
2628  Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
2629  true);
2630  d = d.ashr(ShAmt);
2631  }
2632 
2633  // Calculate the multiplicative inverse, using Newton's method.
2634  APInt t, xn = d;
2635  while ((t = d*xn) != 1)
2636  xn *= APInt(d.getBitWidth(), 2) - t;
2637 
2638  Op2 = DAG.getConstant(xn, Op1.getValueType());
2639  return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2640 }
EVT getShiftAmountTy(EVT LHSTy) const
const APInt & getAPIntValue() const
int d()
assert(Globals.size() > 1)
Class for arbitrary precision integers.
Definition: APInt.h:75
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue TargetLowering::BuildSDIV ( SDNode N,
const APInt Divisor,
SelectionDAG DAG,
bool  IsAfterLegalization,
std::vector< SDNode * > *  Created 
) const
inherited

Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html

Definition at line 2646 of file TargetLowering.cpp.

2648  {
2649  EVT VT = N->getValueType(0);
2650  SDLoc dl(N);
2651 
2652  // Check to see if we can do this.
2653  // FIXME: We should be more aggressive here.
2654  if (!isTypeLegal(VT))
2655  return SDValue();
2656 
2657  APInt::ms magics = Divisor.magic();
2658 
2659  // Multiply the numerator (operand 0) by the magic value
2660  // FIXME: We should support doing a MUL in a wider type
2661  SDValue Q;
2662  if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2664  Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2665  DAG.getConstant(magics.m, VT));
2666  else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2668  Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2669  N->getOperand(0),
2670  DAG.getConstant(magics.m, VT)).getNode(), 1);
2671  else
2672  return SDValue(); // No mulhs or equvialent
2673  // If d > 0 and m < 0, add the numerator
2674  if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2675  Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2676  if (Created)
2677  Created->push_back(Q.getNode());
2678  }
2679  // If d < 0 and m > 0, subtract the numerator.
2680  if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2681  Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2682  if (Created)
2683  Created->push_back(Q.getNode());
2684  }
2685  // Shift right algebraic if shift value is nonzero
2686  if (magics.s > 0) {
2687  Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2688  DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2689  if (Created)
2690  Created->push_back(Q.getNode());
2691  }
2692  // Extract the sign bit and add it to the quotient
2693  SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2694  DAG.getConstant(VT.getScalarSizeInBits() - 1,
2696  if (Created)
2697  Created->push_back(T.getNode());
2698  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2699 }
unsigned s
shift amount
Definition: APInt.h:1699
const SDValue & getOperand(unsigned Num) const
ms magic() const
Definition: APInt.cpp:1396
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:320
EVT getShiftAmountTy(EVT LHSTy) const
EVT getValueType(unsigned ResNo) const
SDVTList getVTList(EVT VT)
#define T
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:240
bool isTypeLegal(EVT VT) const
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
bool isStrictlyPositive() const
Determine if this APInt Value is positive.
Definition: APInt.h:333
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Magic data for optimising signed division by a constant.
Definition: APInt.h:1697
APInt m
magic number
Definition: APInt.h:1698
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue TargetLowering::BuildUDIV ( SDNode N,
const APInt Divisor,
SelectionDAG DAG,
bool  IsAfterLegalization,
std::vector< SDNode * > *  Created 
) const
inherited

Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html

Definition at line 2705 of file TargetLowering.cpp.

2707  {
2708  EVT VT = N->getValueType(0);
2709  SDLoc dl(N);
2710 
2711  // Check to see if we can do this.
2712  // FIXME: We should be more aggressive here.
2713  if (!isTypeLegal(VT))
2714  return SDValue();
2715 
2716  // FIXME: We should use a narrower constant when the upper
2717  // bits are known to be zero.
2718  APInt::mu magics = Divisor.magicu();
2719 
2720  SDValue Q = N->getOperand(0);
2721 
2722  // If the divisor is even, we can avoid using the expensive fixup by shifting
2723  // the divided value upfront.
2724  if (magics.a != 0 && !Divisor[0]) {
2725  unsigned Shift = Divisor.countTrailingZeros();
2726  Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2727  DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
2728  if (Created)
2729  Created->push_back(Q.getNode());
2730 
2731  // Get magic number for the shifted divisor.
2732  magics = Divisor.lshr(Shift).magicu(Shift);
2733  assert(magics.a == 0 && "Should use cheap fixup now");
2734  }
2735 
2736  // Multiply the numerator (operand 0) by the magic value
2737  // FIXME: We should support doing a MUL in a wider type
2738  if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2740  Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2741  else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2743  Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2744  DAG.getConstant(magics.m, VT)).getNode(), 1);
2745  else
2746  return SDValue(); // No mulhu or equvialent
2747  if (Created)
2748  Created->push_back(Q.getNode());
2749 
2750  if (magics.a == 0) {
2751  assert(magics.s < Divisor.getBitWidth() &&
2752  "We shouldn't generate an undefined shift!");
2753  return DAG.getNode(ISD::SRL, dl, VT, Q,
2754  DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2755  } else {
2756  SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2757  if (Created)
2758  Created->push_back(NPQ.getNode());
2759  NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2760  DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
2761  if (Created)
2762  Created->push_back(NPQ.getNode());
2763  NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2764  if (Created)
2765  Created->push_back(NPQ.getNode());
2766  return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2767  DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
2768  }
2769 }
mu magicu(unsigned LeadingZeros=0) const
Definition: APInt.cpp:1440
const SDValue & getOperand(unsigned Num) const
Magic data for optimising unsigned division by a constant.
Definition: APInt.h:1703
EVT getShiftAmountTy(EVT LHSTy) const
EVT getValueType(unsigned ResNo) const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
SDVTList getVTList(EVT VT)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.cpp:737
APInt m
magic number
Definition: APInt.h:1704
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned s
shift amount
Definition: APInt.h:1706
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
bool a
add indicator
Definition: APInt.h:1705
bool ARMTargetLowering::CanLowerReturn ( CallingConv::ID  CallConv,
MachineFunction MF,
bool  isVarArg,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
LLVMContext Context 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2047 of file ARMISelLowering.cpp.

2050  {
2052  CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2053  return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2054  isVarArg));
2055 }
const TargetMachine & getTargetMachine() const
CCAssignFn * CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const
bool TargetLoweringBase::canOpTrap ( unsigned  Op,
EVT  VT 
) const
virtualinherited

Returns true if the operation can trap for the value type.

VT must be a legal type. By default, we optimistically assume most operations don't trap except for divide and remainder.

canOpTrap - Returns true if the operation can trap for the value type. VT must be a legal type.

Definition at line 869 of file TargetLoweringBase.cpp.

869  {
870  assert(isTypeLegal(VT));
871  switch (Op) {
872  default:
873  return false;
874  case ISD::FDIV:
875  case ISD::FREM:
876  case ISD::SDIV:
877  case ISD::UDIV:
878  case ISD::SREM:
879  case ISD::UREM:
880  return true;
881  }
882 }
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
CCAssignFn * ARMTargetLowering::CCAssignFnForNode ( CallingConv::ID  CC,
bool  Return,
bool  isVarArg 
) const
private

CCAssignFnForNode - Selects the correct CCAssignFn for the given CallingConvention.

Definition at line 1239 of file ARMISelLowering.cpp.

1241  {
1242  switch (getEffectiveCallingConv(CC, isVarArg)) {
1243  default:
1244  llvm_unreachable("Unsupported calling convention");
1245  case CallingConv::ARM_APCS:
1246  return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1248  return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1250  return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1251  case CallingConv::Fast:
1252  return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1253  case CallingConv::GHC:
1254  return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1255  }
1256 }
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:93
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC, bool isVarArg) const
Instr is a return instruction.
Definition: GCMetadata.h:54
void llvm::TargetLoweringBase::clearOperationActions ( )
inlineprotectedinherited

Remove all operation actions.

Definition at line 1088 of file TargetLowering.h.

1088  {
1089  }
void llvm::TargetLoweringBase::clearRegisterClasses ( )
inlineprotectedinherited

Remove all register classes.

Definition at line 1081 of file TargetLowering.h.

1081  {
1082  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1083 
1084  AvailableRegClasses.clear();
1085  }
std::vector< std::pair< MVT, const TargetRegisterClass * > > AvailableRegClasses
True if this is a little endian target.
void *memset(void *b, int c, size_t len);
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
void TargetLowering::ComputeConstraintToUse ( AsmOperandInfo OpInfo,
SDValue  Op,
SelectionDAG DAG = nullptr 
) const
virtualinherited

Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand being passed in is available, it can be passed in as Op, otherwise an empty SDValue can be passed.

ComputeConstraintToUse - Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.

Definition at line 2582 of file TargetLowering.cpp.

2584  {
2585  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2586 
2587  // Single-letter constraints ('r') are very common.
2588  if (OpInfo.Codes.size() == 1) {
2589  OpInfo.ConstraintCode = OpInfo.Codes[0];
2590  OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2591  } else {
2592  ChooseConstraint(OpInfo, *this, Op, DAG);
2593  }
2594 
2595  // 'X' matches anything.
2596  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2597  // Labels and constants are handled elsewhere ('X' is the only thing
2598  // that matches labels). For Functions, the type here is the type of
2599  // the result, which is not what we want to look at; leave them alone.
2600  Value *v = OpInfo.CallOperandVal;
2601  if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2602  OpInfo.CallOperandVal = v;
2603  return;
2604  }
2605 
2606  // Otherwise, try to resolve it to something we know about by looking at
2607  // the actual operand type.
2608  if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2609  OpInfo.ConstraintCode = Repl;
2610  OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2611  }
2612  }
2613 }
virtual ConstraintType getConstraintType(const std::string &Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual const char * LowerXConstraint(EVT ConstraintVT) const
assert(Globals.size() > 1)
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG)
LLVM Value Representation.
Definition: Value.h:69
void ARMTargetLowering::computeKnownBitsForTargetNode ( const SDValue  Op,
APInt KnownZero,
APInt KnownOne,
const SelectionDAG DAG,
unsigned  Depth 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 10203 of file ARMISelLowering.cpp.

10207  {
10208  unsigned BitWidth = KnownOne.getBitWidth();
10209  KnownZero = KnownOne = APInt(BitWidth, 0);
10210  switch (Op.getOpcode()) {
10211  default: break;
10212  case ARMISD::ADDC:
10213  case ARMISD::ADDE:
10214  case ARMISD::SUBC:
10215  case ARMISD::SUBE:
10216  // These nodes' second result is a boolean
10217  if (Op.getResNo() == 0)
10218  break;
10219  KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10220  break;
10221  case ARMISD::CMOV: {
10222  // Bits are known zero/one if known on the LHS and RHS.
10223  DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
10224  if (KnownZero == 0 && KnownOne == 0) return;
10225 
10226  APInt KnownZeroRHS, KnownOneRHS;
10227  DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
10228  KnownZero &= KnownZeroRHS;
10229  KnownOne &= KnownOneRHS;
10230  return;
10231  }
10232  case ISD::INTRINSIC_W_CHAIN: {
10233  ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
10234  Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
10235  switch (IntID) {
10236  default: return;
10237  case Intrinsic::arm_ldaex:
10238  case Intrinsic::arm_ldrex: {
10239  EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
10240  unsigned MemBits = VT.getScalarType().getSizeInBits();
10241  KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
10242  return;
10243  }
10244  }
10245  }
10246  }
10247 }
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
const SDValue & getOperand(unsigned Num) const
unsigned getResNo() const
get the index which selects a specific result in the SDNode
EVT getScalarType() const
Definition: ValueTypes.h:211
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
const SDValue & getOperand(unsigned i) const
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned getOpcode() const
Class for arbitrary precision integers.
Definition: APInt.h:75
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
uint64_t getZExtValue() const
unsigned TargetLowering::ComputeNumSignBitsForTargetNode ( SDValue  Op,
const SelectionDAG DAG,
unsigned  Depth = 0 
) const
virtualinherited

This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

ComputeNumSignBitsForTargetNode - This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1104 of file TargetLowering.cpp.

1106  {
1110  Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1111  "Should use ComputeNumSignBits if you don't know whether Op"
1112  " is a target node!");
1113  return 1;
1114 }
assert(Globals.size() > 1)
unsigned getOpcode() const
void ARMTargetLowering::computeRegArea ( CCState CCInfo,
MachineFunction MF,
unsigned  InRegsParamRecordIdx,
unsigned  ArgSize,
unsigned &  ArgRegsSize,
unsigned &  ArgRegsSaveSize 
) const
private

Definition at line 2734 of file ARMISelLowering.cpp.

2739  {
2740  unsigned NumGPRs;
2741  if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2742  unsigned RBegin, REnd;
2743  CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2744  NumGPRs = REnd - RBegin;
2745  } else {
2746  unsigned int firstUnalloced;
2747  firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2748  sizeof(GPRArgRegs) /
2749  sizeof(GPRArgRegs[0]));
2750  NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2751  }
2752 
2753  unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2754  ArgRegsSize = NumGPRs * 4;
2755 
2756  // If parameter is split between stack and GPRs...
2757  if (NumGPRs && Align > 4 &&
2758  (ArgRegsSize < ArgSize ||
2759  InRegsParamRecordIdx >= CCInfo.getInRegsParamsCount())) {
2760  // Add padding for part of param recovered from GPRs. For example,
2761  // if Align == 8, its last byte must be at address K*8 - 1.
2762  // We need to do it, since remained (stack) part of parameter has
2763  // stack alignment, and we need to "attach" "GPRs head" without gaps
2764  // to it:
2765  // Stack:
2766  // |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
2767  // [ [padding] [GPRs head] ] [ Tail passed via stack ....
2768  //
2770  unsigned Padding =
2771  OffsetToAlignment(ArgRegsSize + AFI->getArgRegsSaveSize(), Align);
2772  ArgRegsSaveSize = ArgRegsSize + Padding;
2773  } else
2774  // We don't need to extend regs save size for byval parameters if they
2775  // are passed via GPRs only.
2776  ArgRegsSaveSize = ArgRegsSize;
2777 }
unsigned getStackAlignment() const
void getInRegsParamInfo(unsigned InRegsParamRecordIndex, unsigned &BeginReg, unsigned &EndReg) const
unsigned getInRegsParamsCount() const
unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const
static const MCPhysReg GPRArgRegs[]
virtual const TargetFrameLowering * getFrameLowering() const
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
const TargetMachine & getTarget() const
uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align)
Definition: MathExtras.h:600
unsigned getArgRegsSaveSize(unsigned Align=0) const
void TargetLoweringBase::computeRegisterProperties ( )
protectedinherited

Once all of the register classes are added, this allows us to compute derived properties we expose.

computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition at line 1025 of file TargetLoweringBase.cpp.

1025  {
1027  "Too many value types for ValueTypeActions to hold!");
1028 
1029  // Everything defaults to needing one register.
1030  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1031  NumRegistersForVT[i] = 1;
1033  }
1034  // ...except isVoid, which doesn't need any registers.
1036 
1037  // Find the largest integer register class.
1038  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1039  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1040  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1041 
1042  // Every integer value type larger than this largest register takes twice as
1043  // many registers to represent as the previous ValueType.
1044  for (unsigned ExpandedReg = LargestIntReg + 1;
1045  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1046  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1047  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1048  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1051  }
1052 
1053  // Inspect all of the ValueType's smaller than the largest integer
1054  // register to see which ones need promotion.
1055  unsigned LegalIntReg = LargestIntReg;
1056  for (unsigned IntReg = LargestIntReg - 1;
1057  IntReg >= (unsigned)MVT::i1; --IntReg) {
1058  MVT IVT = (MVT::SimpleValueType)IntReg;
1059  if (isTypeLegal(IVT)) {
1060  LegalIntReg = IntReg;
1061  } else {
1062  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1063  (const MVT::SimpleValueType)LegalIntReg;
1065  }
1066  }
1067 
1068  // ppcf128 type is really two f64's.
1069  if (!isTypeLegal(MVT::ppcf128)) {
1074  }
1075 
1076  // Decide how to handle f128. If the target does not have native f128 support,
1077  // expand it to i128 and we will be generating soft float library calls.
1078  if (!isTypeLegal(MVT::f128)) {
1083  }
1084 
1085  // Decide how to handle f64. If the target does not have native f64 support,
1086  // expand it to i64 and we will be generating soft float library calls.
1087  if (!isTypeLegal(MVT::f64)) {
1092  }
1093 
1094  // Decide how to handle f32. If the target does not have native support for
1095  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
1096  if (!isTypeLegal(MVT::f32)) {
1097  if (isTypeLegal(MVT::f64)) {
1102  } else {
1107  }
1108  }
1109 
1110  if (!isTypeLegal(MVT::f16)) {
1115  }
1116 
1117  // Loop over all of the vector value types to see which need transformations.
1118  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1119  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1120  MVT VT = (MVT::SimpleValueType) i;
1121  if (isTypeLegal(VT))
1122  continue;
1123 
1124  MVT EltVT = VT.getVectorElementType();
1125  unsigned NElts = VT.getVectorNumElements();
1126  bool IsLegalWiderType = false;
1127  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1128  switch (PreferredAction) {
1129  case TypePromoteInteger: {
1130  // Try to promote the elements of integer vectors. If no legal
1131  // promotion was found, fall through to the widen-vector method.
1132  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1133  MVT SVT = (MVT::SimpleValueType) nVT;
1134  // Promote vectors of integers to vectors with the same number
1135  // of elements, with a wider element type.
1136  if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
1137  && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1138  && SVT.getScalarType().isInteger()) {
1139  TransformToType[i] = SVT;
1140  RegisterTypeForVT[i] = SVT;
1141  NumRegistersForVT[i] = 1;
1143  IsLegalWiderType = true;
1144  break;
1145  }
1146  }
1147  if (IsLegalWiderType)
1148  break;
1149  }
1150  case TypeWidenVector: {
1151  // Try to widen the vector.
1152  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1153  MVT SVT = (MVT::SimpleValueType) nVT;
1154  if (SVT.getVectorElementType() == EltVT
1155  && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1156  TransformToType[i] = SVT;
1157  RegisterTypeForVT[i] = SVT;
1158  NumRegistersForVT[i] = 1;
1160  IsLegalWiderType = true;
1161  break;
1162  }
1163  }
1164  if (IsLegalWiderType)
1165  break;
1166  }
1167  case TypeSplitVector:
1168  case TypeScalarizeVector: {
1169  MVT IntermediateVT;
1170  MVT RegisterVT;
1171  unsigned NumIntermediates;
1172  NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1173  NumIntermediates, RegisterVT, this);
1174  RegisterTypeForVT[i] = RegisterVT;
1175 
1176  MVT NVT = VT.getPow2VectorType();
1177  if (NVT == VT) {
1178  // Type is already a power of 2. The default action is to split.
1180  if (PreferredAction == TypeScalarizeVector)
1182  else
1184  } else {
1185  TransformToType[i] = NVT;
1187  }
1188  break;
1189  }
1190  default:
1191  llvm_unreachable("Unknown vector legalization action!");
1192  }
1193  }
1194 
1195  // Determine the 'representative' register class for each value type.
1196  // An representative register class is the largest (meaning one which is
1197  // not a sub-register class / subreg register class) legal register class for
1198  // a group of value types. For example, on i386, i8, i16, and i32
1199  // representative would be GR32; while on x86_64 it's GR64.
1200  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1201  const TargetRegisterClass* RRC;
1202  uint8_t Cost;
1203  std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
1204  RepRegClassForVT[i] = RRC;
1205  RepRegClassCostForVT[i] = Cost;
1206  }
1207 }
const TargetRegisterClass * RepRegClassForVT[MVT::LAST_VALUETYPE]
MVT TransformToType[MVT::LAST_VALUETYPE]
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(MVT VT) const
unsigned getSizeInBits() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MVT getScalarType() const
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
unsigned getVectorNumElements() const
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
Y = RRC X, rotate right via carry.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
void setTypeAction(MVT VT, LegalizeTypeAction Action)
MVT getPow2VectorType() const
MVT getVectorElementType() const
uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]
FastISel * ARMTargetLowering::createFastISel ( FunctionLoweringInfo funcInfo,
const TargetLibraryInfo libInfo 
) const
overridevirtual

createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Reimplemented from llvm::TargetLowering.

Definition at line 1104 of file ARMISelLowering.cpp.

1105  {
1106  return ARM::createFastISel(funcInfo, libInfo);
1107 }
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
SDValue ARMTargetLowering::duplicateCmp ( SDValue  Cmp,
SelectionDAG DAG 
) const
private

duplicateCmp - Glue values can have only one use, so this function duplicates a comparison node.

Definition at line 3223 of file ARMISelLowering.cpp.

3223  {
3224  unsigned Opc = Cmp.getOpcode();
3225  SDLoc DL(Cmp);
3226  if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3227  return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3228 
3229  assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3230  Cmp = Cmp.getOperand(0);
3231  Opc = Cmp.getOpcode();
3232  if (Opc == ARMISD::CMPFP)
3233  Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3234  else {
3235  assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3236  Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3237  }
3238  return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3239 }
const DataLayout * DL
True if this is a little endian target.
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
MachineBasicBlock * ARMTargetLowering::EmitInstrWithCustomInserter ( MachineInstr MI,
MachineBasicBlock MBB 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 7237 of file ARMISelLowering.cpp.

7238  {
7240  DebugLoc dl = MI->getDebugLoc();
7241  bool isThumb2 = Subtarget->isThumb2();
7242  switch (MI->getOpcode()) {
7243  default: {
7244  MI->dump();
7245  llvm_unreachable("Unexpected instr type to insert");
7246  }
7247  // The Thumb2 pre-indexed stores have the same MI operands, they just
7248  // define them differently in the .td files from the isel patterns, so
7249  // they need pseudos.
7250  case ARM::t2STR_preidx:
7251  MI->setDesc(TII->get(ARM::t2STR_PRE));
7252  return BB;
7253  case ARM::t2STRB_preidx:
7254  MI->setDesc(TII->get(ARM::t2STRB_PRE));
7255  return BB;
7256  case ARM::t2STRH_preidx:
7257  MI->setDesc(TII->get(ARM::t2STRH_PRE));
7258  return BB;
7259 
7260  case ARM::STRi_preidx:
7261  case ARM::STRBi_preidx: {
7262  unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7263  ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7264  // Decode the offset.
7265  unsigned Offset = MI->getOperand(4).getImm();
7266  bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7267  Offset = ARM_AM::getAM2Offset(Offset);
7268  if (isSub)
7269  Offset = -Offset;
7270 
7271  MachineMemOperand *MMO = *MI->memoperands_begin();
7272  BuildMI(*BB, MI, dl, TII->get(NewOpc))
7273  .addOperand(MI->getOperand(0)) // Rn_wb
7274  .addOperand(MI->getOperand(1)) // Rt
7275  .addOperand(MI->getOperand(2)) // Rn
7276  .addImm(Offset) // offset (skip GPR==zero_reg)
7277  .addOperand(MI->getOperand(5)) // pred
7278  .addOperand(MI->getOperand(6))
7279  .addMemOperand(MMO);
7280  MI->eraseFromParent();
7281  return BB;
7282  }
7283  case ARM::STRr_preidx:
7284  case ARM::STRBr_preidx:
7285  case ARM::STRH_preidx: {
7286  unsigned NewOpc;
7287  switch (MI->getOpcode()) {
7288  default: llvm_unreachable("unexpected opcode!");
7289  case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7290  case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7291  case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7292  }
7293  MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7294  for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7295  MIB.addOperand(MI->getOperand(i));
7296  MI->eraseFromParent();
7297  return BB;
7298  }
7299 
7300  case ARM::tMOVCCr_pseudo: {
7301  // To "insert" a SELECT_CC instruction, we actually have to insert the
7302  // diamond control-flow pattern. The incoming instruction knows the
7303  // destination vreg to set, the condition code register to branch on, the
7304  // true/false values to select between, and a branch opcode to use.
7305  const BasicBlock *LLVM_BB = BB->getBasicBlock();
7306  MachineFunction::iterator It = BB;
7307  ++It;
7308 
7309  // thisMBB:
7310  // ...
7311  // TrueVal = ...
7312  // cmpTY ccX, r1, r2
7313  // bCC copy1MBB
7314  // fallthrough --> copy0MBB
7315  MachineBasicBlock *thisMBB = BB;
7316  MachineFunction *F = BB->getParent();
7317  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7318  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7319  F->insert(It, copy0MBB);
7320  F->insert(It, sinkMBB);
7321 
7322  // Transfer the remainder of BB and its successor edges to sinkMBB.
7323  sinkMBB->splice(sinkMBB->begin(), BB,
7324  std::next(MachineBasicBlock::iterator(MI)), BB->end());
7325  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7326 
7327  BB->addSuccessor(copy0MBB);
7328  BB->addSuccessor(sinkMBB);
7329 
7330  BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7331  .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7332 
7333  // copy0MBB:
7334  // %FalseValue = ...
7335  // # fallthrough to sinkMBB
7336  BB = copy0MBB;
7337 
7338  // Update machine-CFG edges
7339  BB->addSuccessor(sinkMBB);
7340 
7341  // sinkMBB:
7342  // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7343  // ...
7344  BB = sinkMBB;
7345  BuildMI(*BB, BB->begin(), dl,
7346  TII->get(ARM::PHI), MI->getOperand(0).getReg())
7347  .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7348  .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7349 
7350  MI->eraseFromParent(); // The pseudo instruction is gone now.
7351  return BB;
7352  }
7353 
7354  case ARM::BCCi64:
7355  case ARM::BCCZi64: {
7356  // If there is an unconditional branch to the other successor, remove it.
7357  BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
7358 
7359  // Compare both parts that make up the double comparison separately for
7360  // equality.
7361  bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7362 
7363  unsigned LHS1 = MI->getOperand(1).getReg();
7364  unsigned LHS2 = MI->getOperand(2).getReg();
7365  if (RHSisZero) {
7366  AddDefaultPred(BuildMI(BB, dl,
7367  TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7368  .addReg(LHS1).addImm(0));
7369  BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7370  .addReg(LHS2).addImm(0)
7371  .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7372  } else {
7373  unsigned RHS1 = MI->getOperand(3).getReg();
7374  unsigned RHS2 = MI->getOperand(4).getReg();
7375  AddDefaultPred(BuildMI(BB, dl,
7376  TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7377  .addReg(LHS1).addReg(RHS1));
7378  BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7379  .addReg(LHS2).addReg(RHS2)
7380  .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7381  }
7382 
7383  MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7384  MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7385  if (MI->getOperand(0).getImm() == ARMCC::NE)
7386  std::swap(destMBB, exitMBB);
7387 
7388  BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7389  .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7390  if (isThumb2)
7391  AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7392  else
7393  BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7394 
7395  MI->eraseFromParent(); // The pseudo instruction is gone now.
7396  return BB;
7397  }
7398 
7399  case ARM::Int_eh_sjlj_setjmp:
7400  case ARM::Int_eh_sjlj_setjmp_nofp:
7401  case ARM::tInt_eh_sjlj_setjmp:
7402  case ARM::t2Int_eh_sjlj_setjmp:
7403  case ARM::t2Int_eh_sjlj_setjmp_nofp:
7404  EmitSjLjDispatchBlock(MI, BB);
7405  return BB;
7406 
7407  case ARM::ABS:
7408  case ARM::t2ABS: {
7409  // To insert an ABS instruction, we have to insert the
7410  // diamond control-flow pattern. The incoming instruction knows the
7411  // source vreg to test against 0, the destination vreg to set,
7412  // the condition code register to branch on, the
7413  // true/false values to select between, and a branch opcode to use.
7414  // It transforms
7415  // V1 = ABS V0
7416  // into
7417  // V2 = MOVS V0
7418  // BCC (branch to SinkBB if V0 >= 0)
7419  // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7420  // SinkBB: V1 = PHI(V2, V3)
7421  const BasicBlock *LLVM_BB = BB->getBasicBlock();
7422  MachineFunction::iterator BBI = BB;
7423  ++BBI;
7424  MachineFunction *Fn = BB->getParent();
7425  MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7426  MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7427  Fn->insert(BBI, RSBBB);
7428  Fn->insert(BBI, SinkBB);
7429 
7430  unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7431  unsigned int ABSDstReg = MI->getOperand(0).getReg();
7432  bool isThumb2 = Subtarget->isThumb2();
7433  MachineRegisterInfo &MRI = Fn->getRegInfo();
7434  // In Thumb mode S must not be specified if source register is the SP or
7435  // PC and if destination register is the SP, so restrict register class
7436  unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
7437  (const TargetRegisterClass*)&ARM::rGPRRegClass :
7438  (const TargetRegisterClass*)&ARM::GPRRegClass);
7439 
7440  // Transfer the remainder of BB and its successor edges to sinkMBB.
7441  SinkBB->splice(SinkBB->begin(), BB,
7442  std::next(MachineBasicBlock::iterator(MI)), BB->end());
7443  SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7444 
7445  BB->addSuccessor(RSBBB);
7446  BB->addSuccessor(SinkBB);
7447 
7448  // fall through to SinkMBB
7449  RSBBB->addSuccessor(SinkBB);
7450 
7451  // insert a cmp at the end of BB
7452  AddDefaultPred(BuildMI(BB, dl,
7453  TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7454  .addReg(ABSSrcReg).addImm(0));
7455 
7456  // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7457  BuildMI(BB, dl,
7458  TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7460 
7461  // insert rsbri in RSBBB
7462  // Note: BCC and rsbri will be converted into predicated rsbmi
7463  // by if-conversion pass
7464  BuildMI(*RSBBB, RSBBB->begin(), dl,
7465  TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7466  .addReg(ABSSrcReg, RegState::Kill)
7467  .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7468 
7469  // insert PHI in SinkBB,
7470  // reuse ABSDstReg to not change uses of ABS instruction
7471  BuildMI(*SinkBB, SinkBB->begin(), dl,
7472  TII->get(ARM::PHI), ABSDstReg)
7473  .addReg(NewRsbDstReg).addMBB(RSBBB)
7474  .addReg(ABSSrcReg).addMBB(BB);
7475 
7476  // remove ABS instruction
7477  MI->eraseFromParent();
7478 
7479  // return last added BB
7480  return SinkBB;
7481  }
7482  case ARM::COPY_STRUCT_BYVAL_I32:
7483  ++NumLoopByVals;
7484  return EmitStructByval(MI, BB);
7485  case ARM::WIN__CHKSTK:
7486  return EmitLowered__chkstk(MI, BB);
7487  }
7488 }
MachineBasicBlock * getMBB() const
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
MachineBasicBlock * EmitStructByval(MachineInstr *MI, MachineBasicBlock *MBB) const
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
F(f)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const HexagonInstrInfo * TII
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
const MachineInstrBuilder & addImm(int64_t Val) const
unsigned getNumOperands() const
Definition: MachineInstr.h:274
MachineBasicBlock * EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const
int getOpcode() const
Definition: MachineInstr.h:270
int64_t getImm() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
MachineBasicBlock * EmitLowered__chkstk(MachineInstr *MI, MachineBasicBlock *MBB) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
static AddrOpc getAM2Op(unsigned AM2Opc)
virtual const TargetInstrInfo * getInstrInfo() const
void setDesc(const MCInstrDesc &tid)
static unsigned getAM2Offset(unsigned AM2Opc)
const ARMSubtarget * Subtarget
void dump() const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
static CondCodes getOppositeCondition(CondCodes CC)
Definition: ARMBaseInfo.h:47
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
MachineRegisterInfo & getRegInfo()
bool isThumb2() const
Definition: ARMSubtarget.h:402
bool isSub(Instruction *instr)
unsigned getReg() const
getReg - Returns the register number.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
static MachineBasicBlock * OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:339
Value * ARMTargetLowering::emitLoadLinked ( IRBuilder<> &  Builder,
Value Addr,
AtomicOrdering  Ord 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10807 of file ARMISelLowering.cpp.

10808  {
10809  Module *M = Builder.GetInsertBlock()->getParent()->getParent();
10810  Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
10811  bool IsAcquire =
10812  Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent;
10813 
10814  // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
10815  // intrinsic must return {i32, i32} and we have to recombine them into a
10816  // single i64 here.
10817  if (ValTy->getPrimitiveSizeInBits() == 64) {
10818  Intrinsic::ID Int =
10819  IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
10820  Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
10821 
10822  Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
10823  Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
10824 
10825  Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
10826  Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
10827  if (!Subtarget->isLittle())
10828  std::swap (Lo, Hi);
10829  Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
10830  Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
10831  return Builder.CreateOr(
10832  Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
10833  }
10834 
10835  Type *Tys[] = { Addr->getType() };
10836  Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
10837  Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
10838 
10839  return Builder.CreateTruncOrBitCast(
10840  Builder.CreateCall(Ldrex, Addr),
10841  cast<PointerType>(Addr->getType())->getElementType());
10842 }
The main container class for the LLVM Intermediate Representation.
Definition: Module.h:115
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:118
Value * CreateExtractValue(Value *Agg, ArrayRef< unsigned > Idxs, const Twine &Name="")
Definition: IRBuilder.h:1416
bool isLittle() const
Definition: ARMSubtarget.h:420
Value * CreateOr(Value *LHS, Value *RHS, const Twine &Name="")
Definition: IRBuilder.h:822
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=None)
Definition: Function.cpp:737
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:278
Value * CreateZExt(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1097
Value * CreateBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1158
Type * getType() const
Definition: Value.h:215
const ARMSubtarget * Subtarget
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:77
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
Definition: Constants.cpp:528
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
Value * CreateTruncOrBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1182
Value * CreateShl(Value *LHS, Value *RHS, const Twine &Name="", bool HasNUW=false, bool HasNSW=false)
Definition: IRBuilder.h:751
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:336
LLVM Value Representation.
Definition: Value.h:69
CallInst * CreateCall(Value *Callee, const Twine &Name="")
Definition: IRBuilder.h:1345
LLVMContext & getContext() const
Definition: Module.h:253
MachineBasicBlock * ARMTargetLowering::EmitLowered__chkstk ( MachineInstr MI,
MachineBasicBlock MBB 
) const
private

Definition at line 7171 of file ARMISelLowering.cpp.

7172  {
7173  const TargetMachine &TM = getTargetMachine();
7174  const TargetInstrInfo &TII = *TM.getInstrInfo();
7175  DebugLoc DL = MI->getDebugLoc();
7176 
7178  "__chkstk is only supported on Windows");
7179  assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
7180 
7181  // __chkstk takes the number of words to allocate on the stack in R4, and
7182  // returns the stack adjustment in number of bytes in R4. This will not
7183  // clober any other registers (other than the obvious lr).
7184  //
7185  // Although, technically, IP should be considered a register which may be
7186  // clobbered, the call itself will not touch it. Windows on ARM is a pure
7187  // thumb-2 environment, so there is no interworking required. As a result, we
7188  // do not expect a veneer to be emitted by the linker, clobbering IP.
7189  //
7190  // Each module receives its own copy of __chkstk, so no import thunk is
7191  // required, again, ensuring that IP is not clobbered.
7192  //
7193  // Finally, although some linkers may theoretically provide a trampoline for
7194  // out of range calls (which is quite common due to a 32M range limitation of
7195  // branches for Thumb), we can generate the long-call version via
7196  // -mcmodel=large, alleviating the need for the trampoline which may clobber
7197  // IP.
7198 
7199  switch (TM.getCodeModel()) {
7200  case CodeModel::Small:
7201  case CodeModel::Medium:
7202  case CodeModel::Default:
7203  case CodeModel::Kernel:
7204  BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
7205  .addImm((unsigned)ARMCC::AL).addReg(0)
7206  .addExternalSymbol("__chkstk")
7207  .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7208  .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7209  .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7210  break;
7211  case CodeModel::Large:
7212  case CodeModel::JITDefault: {
7213  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
7214  unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
7215 
7216  BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
7217  .addExternalSymbol("__chkstk");
7218  BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
7219  .addImm((unsigned)ARMCC::AL).addReg(0)
7220  .addReg(Reg, RegState::Kill)
7221  .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7222  .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7223  .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7224  break;
7225  }
7226  }
7227 
7228  AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7229  ARM::SP)
7230  .addReg(ARM::SP).addReg(ARM::R4)));
7231 
7232  MI->eraseFromParent();
7233  return MBB;
7234 }
const MachineFunction * getParent() const
#define R4(n)
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
const TargetMachine & TM
True if this is a little endian target.
setjmp/longjmp based exceptions
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const HexagonInstrInfo * TII
Reg
All possible values of the reg field in the ModR/M byte.
const DataLayout * DL
True if this is a little endian target.
assert(Globals.size() > 1)
CodeModel::Model getCodeModel() const
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
virtual const TargetInstrInfo * getInstrInfo() const
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
const ARMSubtarget * Subtarget
MachineRegisterInfo & getRegInfo()
bool isThumb2() const
Definition: ARMSubtarget.h:402
bool isTargetWindows() const
Definition: ARMSubtarget.h:351
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
MachineBasicBlock * TargetLoweringBase::emitPatchPoint ( MachineInstr MI,
MachineBasicBlock MBB 
) const
protectedinherited

Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.

Definition at line 946 of file TargetLoweringBase.cpp.

947  {
948  MachineFunction &MF = *MI->getParent()->getParent();
949 
950  // MI changes inside this loop as we grow operands.
951  for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
952  MachineOperand &MO = MI->getOperand(OperIdx);
953  if (!MO.isFI())
954  continue;
955 
956  // foldMemoryOperand builds a new MI after replacing a single FI operand
957  // with the canonical set of five x86 addressing-mode operands.
958  int FI = MO.getIndex();
959  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
960 
961  // Copy operands before the frame-index.
962  for (unsigned i = 0; i < OperIdx; ++i)
963  MIB.addOperand(MI->getOperand(i));
964  // Add frame index operands: direct-mem-ref tag, #FI, offset.
966  MIB.addOperand(MI->getOperand(OperIdx));
967  MIB.addImm(0);
968  // Copy the operands after the frame index.
969  for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
970  MIB.addOperand(MI->getOperand(i));
971 
972  // Inherit previous memory operands.
973  MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
974  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
975 
976  // Add a new memory operand for this FI.
977  const MachineFrameInfo &MFI = *MF.getFrameInfo();
978  assert(MFI.getObjectOffset(FI) != -1);
979  MachineMemOperand *MMO =
983  MFI.getObjectAlignment(FI));
984  MIB->addMemOperand(MF, MMO);
985 
986  // Replace the instruction and update the operand index.
987  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
988  OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
989  MI->eraseFromParent();
990  MI = MIB;
991  }
992  return MBB;
993 }
The memory access reads data.
const MachineFunction * getParent() const
const TargetMachine & TM
True if this is a little endian target.
const MCInstrDesc & getDesc() const
Definition: MachineInstr.h:266
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
bool mayLoad(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:520
Abstract Stack Frame Information.
const MachineInstrBuilder & addImm(int64_t Val) const
unsigned getNumOperands() const
Definition: MachineInstr.h:274
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:340
assert(Globals.size() > 1)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
MachineFrameInfo * getFrameInfo()
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
virtual const DataLayout * getDataLayout() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
unsigned getPointerSize(unsigned AS=0) const
Definition: DataLayout.cpp:602
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:339
MachineBasicBlock * ARMTargetLowering::EmitSjLjDispatchBlock ( MachineInstr MI,
MachineBasicBlock MBB 
) const
private

Definition at line 6422 of file ARMISelLowering.cpp.

6422  {
6424  DebugLoc dl = MI->getDebugLoc();
6425  MachineFunction *MF = MBB->getParent();
6426  MachineRegisterInfo *MRI = &MF->getRegInfo();
6427  ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6428  MachineFrameInfo *MFI = MF->getFrameInfo();
6429  int FI = MFI->getFunctionContextIndex();
6430 
6431  const TargetRegisterClass *TRC = Subtarget->isThumb() ?
6432  (const TargetRegisterClass*)&ARM::tGPRRegClass :
6433  (const TargetRegisterClass*)&ARM::GPRnopcRegClass;
6434 
6435  // Get a mapping of the call site numbers to all of the landing pads they're
6436  // associated with.
6438  unsigned MaxCSNum = 0;
6439  MachineModuleInfo &MMI = MF->getMMI();
6440  for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6441  ++BB) {
6442  if (!BB->isLandingPad()) continue;
6443 
6444  // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6445  // pad.
6447  II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6448  if (!II->isEHLabel()) continue;
6449 
6450  MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6451  if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6452 
6453  SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6455  CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6456  CSI != CSE; ++CSI) {
6457  CallSiteNumToLPad[*CSI].push_back(BB);
6458  MaxCSNum = std::max(MaxCSNum, *CSI);
6459  }
6460  break;
6461  }
6462  }
6463 
6464  // Get an ordered list of the machine basic blocks for the jump table.
6465  std::vector<MachineBasicBlock*> LPadList;
6467  LPadList.reserve(CallSiteNumToLPad.size());
6468  for (unsigned I = 1; I <= MaxCSNum; ++I) {
6469  SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6471  II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6472  LPadList.push_back(*II);
6473  InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6474  }
6475  }
6476 
6477  assert(!LPadList.empty() &&
6478  "No landing pad destinations for the dispatch jump table!");
6479 
6480  // Create the jump table and associated information.
6481  MachineJumpTableInfo *JTI =
6483  unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6484  unsigned UId = AFI->createJumpTableUId();
6486 
6487  // Create the MBBs for the dispatch code.
6488 
6489  // Shove the dispatch's address into the return slot in the function context.
6490  MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6491  DispatchBB->setIsLandingPad();
6492 
6494  unsigned trap_opcode;
6495  if (Subtarget->isThumb())
6496  trap_opcode = ARM::tTRAP;
6497  else
6498  trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6499 
6500  BuildMI(TrapBB, dl, TII->get(trap_opcode));
6501  DispatchBB->addSuccessor(TrapBB);
6502 
6503  MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6504  DispatchBB->addSuccessor(DispContBB);
6505 
6506  // Insert and MBBs.
6507  MF->insert(MF->end(), DispatchBB);
6508  MF->insert(MF->end(), DispContBB);
6509  MF->insert(MF->end(), TrapBB);
6510 
6511  // Insert code into the entry block that creates and registers the function
6512  // context.
6513  SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6514 
6515  MachineMemOperand *FIMMOLd =
6519 
6520  MachineInstrBuilder MIB;
6521  MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6522 
6523  const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6524  const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6525 
6526  // Add a register mask with no preserved registers. This results in all
6527  // registers being marked as clobbered.
6528  MIB.addRegMask(RI.getNoPreservedMask());
6529 
6530  unsigned NumLPads = LPadList.size();
6531  if (Subtarget->isThumb2()) {
6532  unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6533  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6534  .addFrameIndex(FI)
6535  .addImm(4)
6536  .addMemOperand(FIMMOLd));
6537 
6538  if (NumLPads < 256) {
6539  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6540  .addReg(NewVReg1)
6541  .addImm(LPadList.size()));
6542  } else {
6543  unsigned VReg1 = MRI->createVirtualRegister(TRC);
6544  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6545  .addImm(NumLPads & 0xFFFF));
6546 
6547  unsigned VReg2 = VReg1;
6548  if ((NumLPads & 0xFFFF0000) != 0) {
6549  VReg2 = MRI->createVirtualRegister(TRC);
6550  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6551  .addReg(VReg1)
6552  .addImm(NumLPads >> 16));
6553  }
6554 
6555  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6556  .addReg(NewVReg1)
6557  .addReg(VReg2));
6558  }
6559 
6560  BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6561  .addMBB(TrapBB)
6562  .addImm(ARMCC::HI)
6563  .addReg(ARM::CPSR);
6564 
6565  unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6566  AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6567  .addJumpTableIndex(MJTI)
6568  .addImm(UId));
6569 
6570  unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6571  AddDefaultCC(
6573  BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6574  .addReg(NewVReg3, RegState::Kill)
6575  .addReg(NewVReg1)
6577 
6578  BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6579  .addReg(NewVReg4, RegState::Kill)
6580  .addReg(NewVReg1)
6581  .addJumpTableIndex(MJTI)
6582  .addImm(UId);
6583  } else if (Subtarget->isThumb()) {
6584  unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6585  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6586  .addFrameIndex(FI)
6587  .addImm(1)
6588  .addMemOperand(FIMMOLd));
6589 
6590  if (NumLPads < 256) {
6591  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6592  .addReg(NewVReg1)
6593  .addImm(NumLPads));
6594  } else {
6597  const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6598 
6599  // MachineConstantPool wants an explicit alignment.
6600  unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6601  if (Align == 0)
6602  Align = getDataLayout()->getTypeAllocSize(C->getType());
6603  unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6604 
6605  unsigned VReg1 = MRI->createVirtualRegister(TRC);
6606  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6607  .addReg(VReg1, RegState::Define)
6608  .addConstantPoolIndex(Idx));
6609  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6610  .addReg(NewVReg1)
6611  .addReg(VReg1));
6612  }
6613 
6614  BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
6615  .addMBB(TrapBB)
6616  .addImm(ARMCC::HI)
6617  .addReg(ARM::CPSR);
6618 
6619  unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6620  AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6621  .addReg(ARM::CPSR, RegState::Define)
6622  .addReg(NewVReg1)
6623  .addImm(2));
6624 
6625  unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6626  AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6627  .addJumpTableIndex(MJTI)
6628  .addImm(UId));
6629 
6630  unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6631  AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6632  .addReg(ARM::CPSR, RegState::Define)
6633  .addReg(NewVReg2, RegState::Kill)
6634  .addReg(NewVReg3));
6635 
6636  MachineMemOperand *JTMMOLd =
6639 
6640  unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6641  AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6642  .addReg(NewVReg4, RegState::Kill)
6643  .addImm(0)
6644  .addMemOperand(JTMMOLd));
6645 
6646  unsigned NewVReg6 = NewVReg5;
6647  if (RelocM == Reloc::PIC_) {
6648  NewVReg6 = MRI->createVirtualRegister(TRC);
6649  AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6650  .addReg(ARM::CPSR, RegState::Define)
6651  .addReg(NewVReg5, RegState::Kill)
6652  .addReg(NewVReg3));
6653  }
6654 
6655  BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
6656  .addReg(NewVReg6, RegState::Kill)
6657  .addJumpTableIndex(MJTI)
6658  .addImm(UId);
6659  } else {
6660  unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6661  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6662  .addFrameIndex(FI)
6663  .addImm(4)
6664  .addMemOperand(FIMMOLd));
6665 
6666  if (NumLPads < 256) {
6667  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6668  .addReg(NewVReg1)
6669  .addImm(NumLPads));
6670  } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
6671  unsigned VReg1 = MRI->createVirtualRegister(TRC);
6672  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6673  .addImm(NumLPads & 0xFFFF));
6674 
6675  unsigned VReg2 = VReg1;
6676  if ((NumLPads & 0xFFFF0000) != 0) {
6677  VReg2 = MRI->createVirtualRegister(TRC);
6678  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6679  .addReg(VReg1)
6680  .addImm(NumLPads >> 16));
6681  }
6682 
6683  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6684  .addReg(NewVReg1)
6685  .addReg(VReg2));
6686  } else {
6687  MachineConstantPool *ConstantPool = MF->getConstantPool();
6688  Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6689  const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6690 
6691  // MachineConstantPool wants an explicit alignment.
6692  unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6693  if (Align == 0)
6694  Align = getDataLayout()->getTypeAllocSize(C->getType());
6695  unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6696 
6697  unsigned VReg1 = MRI->createVirtualRegister(TRC);
6698  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6699  .addReg(VReg1, RegState::Define)
6700  .addConstantPoolIndex(Idx)
6701  .addImm(0));
6702  AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6703  .addReg(NewVReg1)
6704  .addReg(VReg1, RegState::Kill));
6705  }
6706 
6707  BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
6708  .addMBB(TrapBB)
6709  .addImm(ARMCC::HI)
6710  .addReg(ARM::CPSR);
6711 
6712  unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6713  AddDefaultCC(
6714  AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6715  .addReg(NewVReg1)
6717  unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6718  AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6719  .addJumpTableIndex(MJTI)
6720  .addImm(UId));
6721 
6722  MachineMemOperand *JTMMOLd =
6725  unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6727  BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
6728  .addReg(NewVReg3, RegState::Kill)
6729  .addReg(NewVReg4)
6730  .addImm(0)
6731  .addMemOperand(JTMMOLd));
6732 
6733  if (RelocM == Reloc::PIC_) {
6734  BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
6735  .addReg(NewVReg5, RegState::Kill)
6736  .addReg(NewVReg4)
6737  .addJumpTableIndex(MJTI)
6738  .addImm(UId);
6739  } else {
6740  BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
6741  .addReg(NewVReg5, RegState::Kill)
6742  .addJumpTableIndex(MJTI)
6743  .addImm(UId);
6744  }
6745  }
6746 
6747  // Add the jump table entries as successors to the MBB.
6749  for (std::vector<MachineBasicBlock*>::iterator
6750  I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6751  MachineBasicBlock *CurMBB = *I;
6752  if (SeenMBBs.insert(CurMBB))
6753  DispContBB->addSuccessor(CurMBB);
6754  }
6755 
6756  // N.B. the order the invoke BBs are processed in doesn't matter here.
6757  const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
6760  I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
6761  MachineBasicBlock *BB = *I;
6762 
6763  // Remove the landing pad successor from the invoke block and replace it
6764  // with the new dispatch block.
6766  BB->succ_end());
6767  while (!Successors.empty()) {
6768  MachineBasicBlock *SMBB = Successors.pop_back_val();
6769  if (SMBB->isLandingPad()) {
6770  BB->removeSuccessor(SMBB);
6771  MBBLPads.push_back(SMBB);
6772  }
6773  }
6774 
6775  BB->addSuccessor(DispatchBB);
6776 
6777  // Find the invoke call and mark all of the callee-saved registers as
6778  // 'implicit defined' so that they're spilled. This prevents code from
6779  // moving instructions to before the EH block, where they will never be
6780  // executed.
6782  II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6783  if (!II->isCall()) continue;
6784 
6785  DenseMap<unsigned, bool> DefRegs;
6787  OI = II->operands_begin(), OE = II->operands_end();
6788  OI != OE; ++OI) {
6789  if (!OI->isReg()) continue;
6790  DefRegs[OI->getReg()] = true;
6791  }
6792 
6793  MachineInstrBuilder MIB(*MF, &*II);
6794 
6795  for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6796  unsigned Reg = SavedRegs[i];
6797  if (Subtarget->isThumb2() &&
6798  !ARM::tGPRRegClass.contains(Reg) &&
6799  !ARM::hGPRRegClass.contains(Reg))
6800  continue;
6801  if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
6802  continue;
6803  if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
6804  continue;
6805  if (!DefRegs[Reg])
6807  }
6808 
6809  break;
6810  }
6811  }
6812 
6813  // Mark all former landing pads as non-landing pads. The dispatch is the only
6814  // landing pad now.
6816  I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
6817  (*I)->setIsLandingPad(false);
6818 
6819  // The instruction is gone now.
6820  MI->eraseFromParent();
6821 
6822  return MBB;
6823 }
SuperClass::iterator iterator
Definition: SmallVector.h:351
int getFunctionContextIndex() const
The memory access reads data.
const MachineFunction * getParent() const
The machine constant pool.
LLVMContext & getContext() const
Definition: Function.cpp:202
Reloc::Model getRelocationModel() const
static MachinePointerInfo getJumpTable()
void setIsLandingPad(bool V=true)
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
static unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
unsigned getPrefTypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:693
bool insert(PtrType Ptr)
Definition: SmallPtrSet.h:256
const Function * getFunction() const
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:290
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF=nullptr) const override
Code Generation virtual methods...
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
MachineJumpTableInfo * getOrCreateJumpTableInfo(unsigned JTEntryKind)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const HexagonInstrInfo * TII
separate const offset from Split GEPs to a variadic base and a constant offset for better CSE
Reg
All possible values of the reg field in the ModR/M byte.
Abstract Stack Frame Information.
The memory access is volatile.
bool isThumb() const
Definition: ARMSubtarget.h:400
const MachineInstrBuilder & addImm(int64_t Val) const
unsigned createJumpTableIndex(const std::vector< MachineBasicBlock * > &DestBBs)
bool hasCallSiteLandingPad(MCSymbol *Sym)
uint16_t MCPhysReg
reverse_iterator rend()
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
reverse_iterator rbegin()
void SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI) const
assert(Globals.size() > 1)
Type * Int32Ty
LLVM Constant Representation.
Definition: Constant.h:41
const DataLayout * getDataLayout() const
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:622
iterator begin() const
Definition: SmallPtrSet.h:279
MachineConstantPool * getConstantPool()
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
void removeSuccessor(MachineBasicBlock *succ)
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
SmallVectorImpl< unsigned > & getCallSiteLandingPad(MCSymbol *Sym)
virtual const TargetInstrInfo * getInstrInfo() const
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
uint64_t getTypeAllocSize(Type *Ty) const
Definition: DataLayout.h:368
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned char TargetFlags=0) const
const uint32_t * getNoPreservedMask() const
const ARMSubtarget * Subtarget
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
Definition: Constants.cpp:528
MachineFrameInfo * getFrameInfo()
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
bool useNaClTrap() const
Definition: ARMSubtarget.h:339
iterator end() const
Definition: SmallPtrSet.h:282
MachineRegisterInfo & getRegInfo()
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:235
bool isThumb2() const
Definition: ARMSubtarget.h:402
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
#define I(x, y, z)
Definition: MD5.cpp:54
void insert(iterator MBBI, MachineBasicBlock *MBB)
std::reverse_iterator< iterator > reverse_iterator
bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:307
BasicBlockListType::iterator iterator
MachineModuleInfo & getMMI() const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
Value * ARMTargetLowering::emitStoreConditional ( IRBuilder<> &  Builder,
Value Val,
Value Addr,
AtomicOrdering  Ord 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10844 of file ARMISelLowering.cpp.

10846  {
10847  Module *M = Builder.GetInsertBlock()->getParent()->getParent();
10848  bool IsRelease =
10849  Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent;
10850 
10851  // Since the intrinsics must have legal type, the i64 intrinsics take two
10852  // parameters: "i32, i32". We must marshal Val into the appropriate form
10853  // before the call.
10854  if (Val->getType()->getPrimitiveSizeInBits() == 64) {
10855  Intrinsic::ID Int =
10856  IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
10857  Function *Strex = Intrinsic::getDeclaration(M, Int);
10859 
10860  Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
10861  Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
10862  if (!Subtarget->isLittle())
10863  std::swap (Lo, Hi);
10864  Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
10865  return Builder.CreateCall3(Strex, Lo, Hi, Addr);
10866  }
10867 
10868  Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
10869  Type *Tys[] = { Addr->getType() };
10870  Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
10871 
10872  return Builder.CreateCall2(
10873  Strex, Builder.CreateZExtOrBitCast(
10874  Val, Strex->getFunctionType()->getParamType(0)),
10875  Addr);
10876 }
Value * CreateLShr(Value *LHS, Value *RHS, const Twine &Name="", bool isExact=false)
Definition: IRBuilder.h:770
The main container class for the LLVM Intermediate Representation.
Definition: Module.h:115
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:118
bool isLittle() const
Definition: ARMSubtarget.h:420
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=None)
Definition: Function.cpp:737
Type * getParamType(unsigned i) const
Parameter type accessors.
Definition: DerivedTypes.h:128
Type * Int32Ty
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:278
Value * CreateBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1158
Type * getType() const
Definition: Value.h:215
const ARMSubtarget * Subtarget
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:77
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
Value * CreateZExtOrBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1166
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:235
FunctionType * getFunctionType() const
Definition: Function.cpp:206
CallInst * CreateCall2(Value *Callee, Value *Arg1, Value *Arg2, const Twine &Name="")
Definition: IRBuilder.h:1351
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:336
Value * CreateTrunc(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1094
LLVM Value Representation.
Definition: Value.h:69
LLVMContext & getContext() const
Definition: Module.h:253
CallInst * CreateCall3(Value *Callee, Value *Arg1, Value *Arg2, Value *Arg3, const Twine &Name="")
Definition: IRBuilder.h:1356
MachineBasicBlock * ARMTargetLowering::EmitStructByval ( MachineInstr MI,
MachineBasicBlock MBB 
) const
private

Definition at line 6935 of file ARMISelLowering.cpp.

6936  {
6937  // This pseudo instruction has 3 operands: dst, src, size
6938  // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
6939  // Otherwise, we will generate unrolled scalar copies.
6941  const BasicBlock *LLVM_BB = BB->getBasicBlock();
6942  MachineFunction::iterator It = BB;
6943  ++It;
6944 
6945  unsigned dest = MI->getOperand(0).getReg();
6946  unsigned src = MI->getOperand(1).getReg();
6947  unsigned SizeVal = MI->getOperand(2).getImm();
6948  unsigned Align = MI->getOperand(3).getImm();
6949  DebugLoc dl = MI->getDebugLoc();
6950 
6951  MachineFunction *MF = BB->getParent();
6952  MachineRegisterInfo &MRI = MF->getRegInfo();
6953  unsigned UnitSize = 0;
6954  const TargetRegisterClass *TRC = nullptr;
6955  const TargetRegisterClass *VecTRC = nullptr;
6956 
6957  bool IsThumb1 = Subtarget->isThumb1Only();
6958  bool IsThumb2 = Subtarget->isThumb2();
6959 
6960  if (Align & 1) {
6961  UnitSize = 1;
6962  } else if (Align & 2) {
6963  UnitSize = 2;
6964  } else {
6965  // Check whether we can use NEON instructions.
6966  if (!MF->getFunction()->getAttributes().
6967  hasAttribute(AttributeSet::FunctionIndex,
6969  Subtarget->hasNEON()) {
6970  if ((Align % 16 == 0) && SizeVal >= 16)
6971  UnitSize = 16;
6972  else if ((Align % 8 == 0) && SizeVal >= 8)
6973  UnitSize = 8;
6974  }
6975  // Can't use NEON instructions.
6976  if (UnitSize == 0)
6977  UnitSize = 4;
6978  }
6979 
6980  // Select the correct opcode and register class for unit size load/store
6981  bool IsNeon = UnitSize >= 8;
6982  TRC = (IsThumb1 || IsThumb2) ? (const TargetRegisterClass *)&ARM::tGPRRegClass
6983  : (const TargetRegisterClass *)&ARM::GPRRegClass;
6984  if (IsNeon)
6985  VecTRC = UnitSize == 16
6986  ? (const TargetRegisterClass *)&ARM::DPairRegClass
6987  : UnitSize == 8
6988  ? (const TargetRegisterClass *)&ARM::DPRRegClass
6989  : nullptr;
6990 
6991  unsigned BytesLeft = SizeVal % UnitSize;
6992  unsigned LoopSize = SizeVal - BytesLeft;
6993 
6994  if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
6995  // Use LDR and STR to copy.
6996  // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
6997  // [destOut] = STR_POST(scratch, destIn, UnitSize)
6998  unsigned srcIn = src;
6999  unsigned destIn = dest;
7000  for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7001  unsigned srcOut = MRI.createVirtualRegister(TRC);
7002  unsigned destOut = MRI.createVirtualRegister(TRC);
7003  unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7004  emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7005  IsThumb1, IsThumb2);
7006  emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7007  IsThumb1, IsThumb2);
7008  srcIn = srcOut;
7009  destIn = destOut;
7010  }
7011 
7012  // Handle the leftover bytes with LDRB and STRB.
7013  // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7014  // [destOut] = STRB_POST(scratch, destIn, 1)
7015  for (unsigned i = 0; i < BytesLeft; i++) {
7016  unsigned srcOut = MRI.createVirtualRegister(TRC);
7017  unsigned destOut = MRI.createVirtualRegister(TRC);
7018  unsigned scratch = MRI.createVirtualRegister(TRC);
7019  emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7020  IsThumb1, IsThumb2);
7021  emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7022  IsThumb1, IsThumb2);
7023  srcIn = srcOut;
7024  destIn = destOut;
7025  }
7026  MI->eraseFromParent(); // The instruction is gone now.
7027  return BB;
7028  }
7029 
7030  // Expand the pseudo op to a loop.
7031  // thisMBB:
7032  // ...
7033  // movw varEnd, # --> with thumb2
7034  // movt varEnd, #
7035  // ldrcp varEnd, idx --> without thumb2
7036  // fallthrough --> loopMBB
7037  // loopMBB:
7038  // PHI varPhi, varEnd, varLoop
7039  // PHI srcPhi, src, srcLoop
7040  // PHI destPhi, dst, destLoop
7041  // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7042  // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7043  // subs varLoop, varPhi, #UnitSize
7044  // bne loopMBB
7045  // fallthrough --> exitMBB
7046  // exitMBB:
7047  // epilogue to handle left-over bytes
7048  // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7049  // [destOut] = STRB_POST(scratch, destLoop, 1)
7050  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7051  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7052  MF->insert(It, loopMBB);
7053  MF->insert(It, exitMBB);
7054 
7055  // Transfer the remainder of BB and its successor edges to exitMBB.
7056  exitMBB->splice(exitMBB->begin(), BB,
7057  std::next(MachineBasicBlock::iterator(MI)), BB->end());
7058  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7059 
7060  // Load an immediate to varEnd.
7061  unsigned varEnd = MRI.createVirtualRegister(TRC);
7062  if (IsThumb2) {
7063  unsigned Vtmp = varEnd;
7064  if ((LoopSize & 0xFFFF0000) != 0)
7065  Vtmp = MRI.createVirtualRegister(TRC);
7066  AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), Vtmp)
7067  .addImm(LoopSize & 0xFFFF));
7068 
7069  if ((LoopSize & 0xFFFF0000) != 0)
7070  AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
7071  .addReg(Vtmp).addImm(LoopSize >> 16));
7072  } else {
7075  const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7076 
7077  // MachineConstantPool wants an explicit alignment.
7078  unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7079  if (Align == 0)
7080  Align = getDataLayout()->getTypeAllocSize(C->getType());
7081  unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7082 
7083  if (IsThumb1)
7084  AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7085  varEnd, RegState::Define).addConstantPoolIndex(Idx));
7086  else
7087  AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7088  varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7089  }
7090  BB->addSuccessor(loopMBB);
7091 
7092  // Generate the loop body:
7093  // varPhi = PHI(varLoop, varEnd)
7094  // srcPhi = PHI(srcLoop, src)
7095  // destPhi = PHI(destLoop, dst)
7096  MachineBasicBlock *entryBB = BB;
7097  BB = loopMBB;
7098  unsigned varLoop = MRI.createVirtualRegister(TRC);
7099  unsigned varPhi = MRI.createVirtualRegister(TRC);
7100  unsigned srcLoop = MRI.createVirtualRegister(TRC);
7101  unsigned srcPhi = MRI.createVirtualRegister(TRC);
7102  unsigned destLoop = MRI.createVirtualRegister(TRC);
7103  unsigned destPhi = MRI.createVirtualRegister(TRC);
7104 
7105  BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7106  .addReg(varLoop).addMBB(loopMBB)
7107  .addReg(varEnd).addMBB(entryBB);
7108  BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7109  .addReg(srcLoop).addMBB(loopMBB)
7110  .addReg(src).addMBB(entryBB);
7111  BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7112  .addReg(destLoop).addMBB(loopMBB)
7113  .addReg(dest).addMBB(entryBB);
7114 
7115  // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7116  // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7117  unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7118  emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7119  IsThumb1, IsThumb2);
7120  emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7121  IsThumb1, IsThumb2);
7122 
7123  // Decrement loop variable by UnitSize.
7124  if (IsThumb1) {
7125  MachineInstrBuilder MIB =
7126  BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7127  MIB = AddDefaultT1CC(MIB);
7128  MIB.addReg(varPhi).addImm(UnitSize);
7129  AddDefaultPred(MIB);
7130  } else {
7131  MachineInstrBuilder MIB =
7132  BuildMI(*BB, BB->end(), dl,
7133  TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7134  AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7135  MIB->getOperand(5).setReg(ARM::CPSR);
7136  MIB->getOperand(5).setIsDef(true);
7137  }
7138  BuildMI(*BB, BB->end(), dl,
7139  TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7140  .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7141 
7142  // loopMBB can loop back to loopMBB or fall through to exitMBB.
7143  BB->addSuccessor(loopMBB);
7144  BB->addSuccessor(exitMBB);
7145 
7146  // Add epilogue to handle BytesLeft.
7147  BB = exitMBB;
7148  MachineInstr *StartOfExit = exitMBB->begin();
7149 
7150  // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7151  // [destOut] = STRB_POST(scratch, destLoop, 1)
7152  unsigned srcIn = srcLoop;
7153  unsigned destIn = destLoop;
7154  for (unsigned i = 0; i < BytesLeft; i++) {
7155  unsigned srcOut = MRI.createVirtualRegister(TRC);
7156  unsigned destOut = MRI.createVirtualRegister(TRC);
7157  unsigned scratch = MRI.createVirtualRegister(TRC);
7158  emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7159  IsThumb1, IsThumb2);
7160  emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7161  IsThumb1, IsThumb2);
7162  srcIn = srcOut;
7163  destIn = destOut;
7164  }
7165 
7166  MI->eraseFromParent(); // The instruction is gone now.
7167  return BB;
7168 }
The machine constant pool.
LLVMContext & getContext() const
Definition: Function.cpp:202
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
unsigned getPrefTypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:693
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
const Function * getFunction() const
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const HexagonInstrInfo * TII
const MachineInstrBuilder & addImm(int64_t Val) const
bool hasNEON() const
Definition: ARMSubtarget.h:311
int64_t getImm() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
Type * Int32Ty
LLVM Constant Representation.
Definition: Constant.h:41
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
const DataLayout * getDataLayout() const
MachineConstantPool * getConstantPool()
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
virtual const TargetInstrInfo * getInstrInfo() const
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
uint64_t getTypeAllocSize(Type *Ty) const
Definition: DataLayout.h:368
const ARMSubtarget * Subtarget
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
Definition: Constants.cpp:528
static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos, const TargetInstrInfo *TII, DebugLoc dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos, const TargetInstrInfo *TII, DebugLoc dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
MachineRegisterInfo & getRegInfo()
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:235
bool isThumb2() const
Definition: ARMSubtarget.h:402
void setReg(unsigned Reg)
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
unsigned getReg() const
getReg - Returns the register number.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
Disable implicit floating point insts.
Definition: Attributes.h:86
BasicBlockListType::iterator iterator
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
static const MachineInstrBuilder & AddDefaultT1CC(const MachineInstrBuilder &MIB, bool isDead=false)
bool TargetLowering::expandFP_TO_SINT ( SDNode N,
SDValue Result,
SelectionDAG DAG 
) const
inherited

Expand float(f32) to SINT(i64) conversion

Parameters
NNode to expand
Resultoutput after conversion
Returns
True, if the expansion was successful, false otherwise

Definition at line 2889 of file TargetLowering.cpp.

2890  {
2891  EVT VT = Node->getOperand(0).getValueType();
2892  EVT NVT = Node->getValueType(0);
2893  SDLoc dl(SDValue(Node, 0));
2894 
2895  // FIXME: Only f32 to i64 conversions are supported.
2896  if (VT != MVT::f32 || NVT != MVT::i64)
2897  return false;
2898 
2899  // Expand f32 -> i64 conversion
2900  // This algorithm comes from compiler-rt's implementation of fixsfdi:
2901  // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2902  EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2903  VT.getSizeInBits());
2904  SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
2905  SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
2906  SDValue Bias = DAG.getConstant(127, IntVT);
2907  SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
2908  IntVT);
2909  SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
2910  SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
2911 
2912  SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
2913 
2914  SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
2915  DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
2916  DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
2917  SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
2918 
2919  SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
2920  DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
2921  DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
2922  Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
2923 
2924  SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
2925  DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
2926  DAG.getConstant(0x00800000, IntVT));
2927 
2928  R = DAG.getZExtOrTrunc(R, dl, NVT);
2929 
2930 
2931  R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
2932  DAG.getNode(ISD::SHL, dl, NVT, R,
2933  DAG.getZExtOrTrunc(
2934  DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
2935  dl, getShiftAmountTy(IntVT))),
2936  DAG.getNode(ISD::SRL, dl, NVT, R,
2937  DAG.getZExtOrTrunc(
2938  DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
2939  dl, getShiftAmountTy(IntVT))),
2940  ISD::SETGT);
2941 
2942  SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
2943  DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
2944  Sign);
2945 
2946  Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
2947  DAG.getConstant(0, NVT), Ret, ISD::SETLT);
2948  return true;
2949 }
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
Definition: APInt.h:441
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Definition: SelectionDAG.h:716
EVT getShiftAmountTy(EVT LHSTy) const
const DomTreeNodeT * Node
SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
bool ARMTargetLowering::ExpandInlineAsm ( CallInst CI) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 10253 of file ARMISelLowering.cpp.

10253  {
10254  // Looking for "rev" which is V6+.
10255  if (!Subtarget->hasV6Ops())
10256  return false;
10257 
10258  InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10259  std::string AsmStr = IA->getAsmString();
10260  SmallVector<StringRef, 4> AsmPieces;
10261  SplitString(AsmStr, AsmPieces, ";\n");
10262 
10263  switch (AsmPieces.size()) {
10264  default: return false;
10265  case 1:
10266  AsmStr = AsmPieces[0];
10267  AsmPieces.clear();
10268  SplitString(AsmStr, AsmPieces, " \t,");
10269 
10270  // rev $0, $1
10271  if (AsmPieces.size() == 3 &&
10272  AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10273  IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10274  IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10275  if (Ty && Ty->getBitWidth() == 32)
10277  }
10278  break;
10279  }
10280 
10281  return false;
10282 }
const Value * getCalledValue() const
const std::string & getAsmString() const
Definition: InlineAsm.h:86
const std::string & getConstraintString() const
Definition: InlineAsm.h:87
bool hasV6Ops() const
Definition: ARMSubtarget.h:288
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:61
::std::string string
Definition: gtest-port.h:766
Integer representation type.
Definition: DerivedTypes.h:37
void SplitString(StringRef Source, SmallVectorImpl< StringRef > &OutFragments, StringRef Delimiters=" \t\n\v\f\r")
Type * getType() const
Definition: Value.h:215
const ARMSubtarget * Subtarget
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
static bool LowerToByteSwap(CallInst *CI)
bool TargetLowering::expandMUL ( SDNode N,
SDValue Lo,
SDValue Hi,
EVT  HiLoVT,
SelectionDAG DAG,
SDValue  LL = SDValue(),
SDValue  LH = SDValue(),
SDValue  RL = SDValue(),
SDValue  RH = SDValue() 
) const
inherited

Expand a MUL into two nodes. One that computes the high bits of the result and one that computes the low bits.

Parameters
HiLoVTThe value type to use for the Lo and Hi nodes.
LLLow bits of the LHS of the MUL. You can use this parameter if you want to control how low bits are extracted from the LHS.
LHHigh bits of the LHS of the MUL. See LL for meaning.
RLLow bits of the RHS of the MUL. See LL for meaning
RHHigh bits of the RHS of the MUL. See LL for meaning.
Returns
true if the node has been expanded. false if it has not

Definition at line 2786 of file TargetLowering.cpp.

2788  {
2789  EVT VT = N->getValueType(0);
2790  SDLoc dl(N);
2791 
2792  bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2793  bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2794  bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2795  bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2796  if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2797  unsigned OuterBitSize = VT.getSizeInBits();
2798  unsigned InnerBitSize = HiLoVT.getSizeInBits();
2799  unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2800  unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2801 
2802  // LL, LH, RL, and RH must be either all NULL or all set to a value.
2803  assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2804  (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2805 
2806  if (!LL.getNode() && !RL.getNode() &&
2808  LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2809  RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2810  }
2811 
2812  if (!LL.getNode())
2813  return false;
2814 
2815  APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2816  if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2817  DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2818  // The inputs are both zero-extended.
2819  if (HasUMUL_LOHI) {
2820  // We can emit a umul_lohi.
2821  Lo = DAG.getNode(ISD::UMUL_LOHI, dl,
2822  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2823  Hi = SDValue(Lo.getNode(), 1);
2824  return true;
2825  }
2826  if (HasMULHU) {
2827  // We can emit a mulhu+mul.
2828  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2829  Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2830  return true;
2831  }
2832  }
2833  if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2834  // The input values are both sign-extended.
2835  if (HasSMUL_LOHI) {
2836  // We can emit a smul_lohi.
2837  Lo = DAG.getNode(ISD::SMUL_LOHI, dl,
2838  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2839  Hi = SDValue(Lo.getNode(), 1);
2840  return true;
2841  }
2842  if (HasMULHS) {
2843  // We can emit a mulhs+mul.
2844  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2845  Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2846  return true;
2847  }
2848  }
2849 
2850  if (!LH.getNode() && !RH.getNode() &&
2853  unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2854  SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
2855  LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2856  LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2857  RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2858  RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2859  }
2860 
2861  if (!LH.getNode())
2862  return false;
2863 
2864  if (HasUMUL_LOHI) {
2865  // Lo,Hi = umul LHS, RHS.
2866  SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2867  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2868  Lo = UMulLOHI;
2869  Hi = UMulLOHI.getValue(1);
2870  RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2871  LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2872  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2873  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2874  return true;
2875  }
2876  if (HasMULHU) {
2877  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2878  Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2879  RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2880  LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2881  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2882  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2883  return true;
2884  }
2885  }
2886  return false;
2887 }
SDValue getValue(unsigned R) const
const SDValue & getOperand(unsigned Num) const
EVT getShiftAmountTy(EVT LHSTy) const
EVT getValueType(unsigned ResNo) const
SDVTList getVTList(EVT VT)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Class for arbitrary precision integers.
Definition: APInt.h:75
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
std::pair< const TargetRegisterClass *, uint8_t > ARMTargetLowering::findRepresentativeClass ( MVT  VT) const
overrideprotectedvirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 907 of file ARMISelLowering.cpp.

907  {
908  const TargetRegisterClass *RRC = nullptr;
909  uint8_t Cost = 1;
910  switch (VT.SimpleTy) {
911  default:
913  // Use DPR as representative register class for all floating point
914  // and vector types. Since there are 32 SPR registers and 32 DPR registers so
915  // the cost is 1 for both f32 and f64.
916  case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
917  case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
918  RRC = &ARM::DPRRegClass;
919  // When NEON is used for SP, only half of the register file is available
920  // because operations that define both SP and DP results will be constrained
921  // to the VFP2 class (D0-D15). We currently model this constraint prior to
922  // coalescing by double-counting the SP regs. See the FIXME above.
924  Cost = 2;
925  break;
926  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
927  case MVT::v4f32: case MVT::v2f64:
928  RRC = &ARM::DPRRegClass;
929  Cost = 2;
930  break;
931  case MVT::v4i64:
932  RRC = &ARM::DPRRegClass;
933  Cost = 4;
934  break;
935  case MVT::v8i64:
936  RRC = &ARM::DPRRegClass;
937  Cost = 8;
938  break;
939  }
940  return std::make_pair(RRC, Cost);
941 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(MVT VT) const
SimpleValueType SimpleTy
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:315
const ARMSubtarget * Subtarget
Y = RRC X, rotate right via carry.
bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters ( Type Ty,
CallingConv::ID  CallConv,
bool  isVarArg 
) const
overridevirtual

Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv.

Return true if a type is an AAPCS-VFP homogeneous aggregate.

Reimplemented from llvm::TargetLowering.

Definition at line 10938 of file ARMISelLowering.cpp.

10939  {
10940  if (getEffectiveCallingConv(CallConv, isVarArg) !=
10942  return false;
10943 
10944  HABaseType Base = HA_UNKNOWN;
10945  uint64_t Members = 0;
10946  bool result = isHomogeneousAggregate(Ty, Base, Members);
10947  DEBUG(dbgs() << "isHA: " << result << " "; Ty->dump(); dbgs() << "\n");
10948  return result;
10949 }
void dump() const
Definition: AsmWriter.cpp:2305
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:93
static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base, uint64_t &Members)
static std::vector< std::string > Members
Definition: llvm-ar.cpp:135
CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC, bool isVarArg) const
#define DEBUG(X)
raw_ostream & dbgs()
dbgs - Return a circular-buffered debug stream.
virtual bool llvm::TargetLoweringBase::GetAddrModeArguments ( IntrinsicInst ,
SmallVectorImpl< Value * > &  ,
Type *&   
) const
inlinevirtualinherited

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.

Definition at line 1236 of file TargetLowering.h.

1238  {
1239  return false;
1240  }
SDValue ARMTargetLowering::getARMCmp ( SDValue  LHS,
SDValue  RHS,
ISD::CondCode  CC,
SDValue ARMcc,
SelectionDAG DAG,
SDLoc  dl 
) const
private

Returns appropriate ARM CMP (cmp) and corresponding condition code for the given operands.

Definition at line 3151 of file ARMISelLowering.cpp.

3153  {
3154  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3155  unsigned C = RHSC->getZExtValue();
3156  if (!isLegalICmpImmediate(C)) {
3157  // Constant does not fit, try adjusting it by one?
3158  switch (CC) {
3159  default: break;
3160  case ISD::SETLT:
3161  case ISD::SETGE:
3162  if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3163  CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3164  RHS = DAG.getConstant(C-1, MVT::i32);
3165  }
3166  break;
3167  case ISD::SETULT:
3168  case ISD::SETUGE:
3169  if (C != 0 && isLegalICmpImmediate(C-1)) {
3170  CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3171  RHS = DAG.getConstant(C-1, MVT::i32);
3172  }
3173  break;
3174  case ISD::SETLE:
3175  case ISD::SETGT:
3176  if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3177  CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3178  RHS = DAG.getConstant(C+1, MVT::i32);
3179  }
3180  break;
3181  case ISD::SETULE:
3182  case ISD::SETUGT:
3183  if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3184  CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3185  RHS = DAG.getConstant(C+1, MVT::i32);
3186  }
3187  break;
3188  }
3189  }
3190  }
3191 
3193  ARMISD::NodeType CompareType;
3194  switch (CondCode) {
3195  default:
3196  CompareType = ARMISD::CMP;
3197  break;
3198  case ARMCC::EQ:
3199  case ARMCC::NE:
3200  // Uses only Z Flag
3201  CompareType = ARMISD::CMPZ;
3202  break;
3203  }
3204  ARMcc = DAG.getConstant(CondCode, MVT::i32);
3205  return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3206 }
SDNode * getNode() const
get the SDNode which holds the desired result
static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC)
IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
bool isLegalICmpImmediate(int64_t Imm) const override
std::pair< SDValue, SDValue > ARMTargetLowering::getARMXALUOOp ( SDValue  Op,
SelectionDAG DAG,
SDValue ARMcc 
) const
private

Definition at line 3242 of file ARMISelLowering.cpp.

3243  {
3244  assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3245 
3246  SDValue Value, OverflowCmp;
3247  SDValue LHS = Op.getOperand(0);
3248  SDValue RHS = Op.getOperand(1);
3249 
3250 
3251  // FIXME: We are currently always generating CMPs because we don't support
3252  // generating CMN through the backend. This is not as good as the natural
3253  // CMP case because it causes a register dependency and cannot be folded
3254  // later.
3255 
3256  switch (Op.getOpcode()) {
3257  default:
3258  llvm_unreachable("Unknown overflow instruction!");
3259  case ISD::SADDO:
3260  ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3261  Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3262  OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3263  break;
3264  case ISD::UADDO:
3265  ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3266  Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3267  OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3268  break;
3269  case ISD::SSUBO:
3270  ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3271  Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3272  OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3273  break;
3274  case ISD::USUBO:
3275  ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3276  Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3277  OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3278  break;
3279  } // switch (...)
3280 
3281  return std::make_pair(Value, OverflowCmp);
3282 }
Same for subtraction.
Definition: ISDOpcodes.h:221
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
static int Value(bit_value_t V)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
BooleanContent llvm::TargetLoweringBase::getBooleanContents ( bool  isVec,
bool  isFloat 
) const
inlineinherited

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.

"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.

Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.

Definition at line 290 of file TargetLowering.h.

290  {
291  if (isVec)
292  return BooleanVectorContents;
293  return isFloat ? BooleanFloatContents : BooleanContents;
294  }
BooleanContent BooleanVectorContents
BooleanContent BooleanFloatContents
BooleanContent BooleanContents
BooleanContent llvm::TargetLoweringBase::getBooleanContents ( EVT  Type) const
inlineinherited

Definition at line 296 of file TargetLowering.h.

296  {
297  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
298  }
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
RelocType Type
Definition: COFFYAML.cpp:285
const DenseMap<unsigned int, unsigned int>& llvm::TargetLoweringBase::getBypassSlowDivWidths ( ) const
inlineinherited

Returns map of slow types for division or remainder with corresponding fast types

Definition at line 222 of file TargetLowering.h.

222  {
223  return BypassSlowDivWidths;
224  }
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
unsigned TargetLoweringBase::getByValTypeAlignment ( Type Ty) const
virtualinherited

Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. This is the actual alignment, not its logarithm.

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. This is the actual alignment, not its logarithm.

Reimplemented in llvm::X86TargetLowering, and llvm::PPCTargetLowering.

Definition at line 1345 of file TargetLoweringBase.cpp.

1345  {
1346  return DL->getABITypeAlignment(Ty);
1347 }
const DataLayout * DL
True if this is a little endian target.
unsigned getABITypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:683
virtual const char* llvm::TargetLowering::getClearCacheBuiltinName ( ) const
inlinevirtualinherited

Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call

Reimplemented in llvm::X86TargetLowering.

Definition at line 2310 of file TargetLowering.h.

2310  {
2311  return "__clear_cache";
2312  }
ISD::CondCode llvm::TargetLoweringBase::getCmpLibcallCC ( RTLIB::Libcall  Call) const
inlineinherited

Get the CondCode that's to be used to test the result of the comparison libcall against zero.

Definition at line 1437 of file TargetLowering.h.

1437  {
1438  return CmpLibcallCCs[Call];
1439  }
ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]
MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType ( ) const
virtualinherited

Return the ValueType for comparison libcalls. Comparions libcalls include floating point comparion calls, and Ordered/Unordered check calls on floating point numbers.

Definition at line 1214 of file TargetLoweringBase.cpp.

1214  {
1215  return MVT::i32; // return the default value
1216 }
LegalizeAction llvm::TargetLoweringBase::getCondCodeAction ( ISD::CondCode  CC,
MVT  VT 
) const
inlineinherited

Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 589 of file TargetLowering.h.

589  {
590  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
591  ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
592  "Table isn't big enough!");
593  // See setCondCodeAction for how this is encoded.
594  uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
595  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
596  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
597  assert(Action != Promote && "Can't promote condition code!");
598  return Action;
599  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
static int Value(bit_value_t V)
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
ARMTargetLowering::ConstraintType ARMTargetLowering::getConstraintType ( const std::string &  Constraint) const
overridevirtual

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

Reimplemented from llvm::TargetLowering.

Definition at line 10287 of file ARMISelLowering.cpp.

10287  {
10288  if (Constraint.size() == 1) {
10289  switch (Constraint[0]) {
10290  default: break;
10291  case 'l': return C_RegisterClass;
10292  case 'w': return C_RegisterClass;
10293  case 'h': return C_RegisterClass;
10294  case 'x': return C_RegisterClass;
10295  case 't': return C_RegisterClass;
10296  case 'j': return C_Other; // Constant for movw.
10297  // An address with a single base register. Due to the way we
10298  // currently handle addresses it is the same as an 'r' memory constraint.
10299  case 'Q': return C_Memory;
10300  }
10301  } else if (Constraint.size() == 2) {
10302  switch (Constraint[0]) {
10303  default: break;
10304  // All 'U+' constraints are addresses.
10305  case 'U': return C_Memory;
10306  }
10307  }
10308  return TargetLowering::getConstraintType(Constraint);
10309 }
virtual ConstraintType getConstraintType(const std::string &Constraint) const
Given a constraint, return the type of constraint it is for this target.
const DataLayout* llvm::TargetLoweringBase::getDataLayout ( ) const
inlineinherited

Definition at line 150 of file TargetLowering.h.

150 { return DL; }
const DataLayout * DL
True if this is a little endian target.
CallingConv::ID ARMTargetLowering::getEffectiveCallingConv ( CallingConv::ID  CC,
bool  isVarArg 
) const
private

getEffectiveCallingConv - Get the effective calling convention, taking into account presence of floating point hardware and calling convention limitations, such as support for variadic functions.

Definition at line 1205 of file ARMISelLowering.cpp.

1206  {
1207  switch (CC) {
1208  default:
1209  llvm_unreachable("Unsupported calling convention");
1211  case CallingConv::ARM_APCS:
1212  case CallingConv::GHC:
1213  return CC;
1216  case CallingConv::C:
1217  if (!Subtarget->isAAPCS_ABI())
1218  return CallingConv::ARM_APCS;
1219  else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1221  !isVarArg)
1223  else
1224  return CallingConv::ARM_AAPCS;
1225  case CallingConv::Fast:
1226  if (!Subtarget->isAAPCS_ABI()) {
1227  if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1228  return CallingConv::Fast;
1229  return CallingConv::ARM_APCS;
1230  } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1232  else
1233  return CallingConv::ARM_AAPCS;
1234  }
1235 }
const TargetMachine & getTargetMachine() const
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:93
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
const ARMSubtarget * Subtarget
bool hasVFP2() const
Definition: ARMSubtarget.h:307
bool isAAPCS_ABI() const
Definition: ARMSubtarget.h:395
FloatABI::ABIType FloatABIType
unsigned llvm::TargetLoweringBase::getExceptionPointerRegister ( ) const
inlineinherited

If a physical register, this returns the register that receives the exception address on entry to a landing pad.

Definition at line 845 of file TargetLowering.h.

845  {
847  }
unsigned llvm::TargetLoweringBase::getExceptionSelectorRegister ( ) const
inlineinherited

If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.

Definition at line 851 of file TargetLowering.h.

851  {
853  }
static ISD::NodeType llvm::TargetLoweringBase::getExtendForContent ( BooleanContent  Content)
inlinestaticinherited

Definition at line 124 of file TargetLowering.h.

124  {
125  switch (Content) {
127  // Extend by adding rubbish bits.
128  return ISD::ANY_EXTEND;
130  // Extend by adding zero bits.
131  return ISD::ZERO_EXTEND;
133  // Extend by copying the sign bit.
134  return ISD::SIGN_EXTEND;
135  }
136  llvm_unreachable("Invalid content kind");
137  }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
SDValue ARMTargetLowering::GetF64FormalArgument ( CCValAssign VA,
CCValAssign NextVA,
SDValue Root,
SelectionDAG DAG,
SDLoc  dl 
) const
private

Definition at line 2698 of file ARMISelLowering.cpp.

2700  {
2701  MachineFunction &MF = DAG.getMachineFunction();
2703 
2704  const TargetRegisterClass *RC;
2705  if (AFI->isThumb1OnlyFunction())
2706  RC = &ARM::tGPRRegClass;
2707  else
2708  RC = &ARM::GPRRegClass;
2709 
2710  // Transform the arguments stored in physical registers into virtual ones.
2711  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2712  SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2713 
2714  SDValue ArgValue2;
2715  if (NextVA.isMemLoc()) {
2716  MachineFrameInfo *MFI = MF.getFrameInfo();
2717  int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2718 
2719  // Create load node to retrieve arguments from the stack.
2720  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2721  ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2723  false, false, false, 0);
2724  } else {
2725  Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2726  ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2727  }
2728  if (!Subtarget->isLittle())
2729  std::swap (ArgValue, ArgValue2);
2730  return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2731 }
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Reg
All possible values of the reg field in the ModR/M byte.
Abstract Stack Frame Information.
bool isLittle() const
Definition: ARMSubtarget.h:420
virtual MVT getPointerTy(uint32_t=0) const
unsigned getLocReg() const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
const ARMSubtarget * Subtarget
MachineFrameInfo * getFrameInfo()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
bool isMemLoc() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
unsigned getLocMemOffset() const
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
LegalizeAction llvm::TargetLoweringBase::getIndexedLoadAction ( unsigned  IdxMode,
MVT  VT 
) const
inlineinherited

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 553 of file TargetLowering.h.

553  {
555  "Table isn't big enough!");
556  unsigned Ty = (unsigned)VT.SimpleTy;
557  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
558  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
assert(Globals.size() > 1)
LegalizeAction llvm::TargetLoweringBase::getIndexedStoreAction ( unsigned  IdxMode,
MVT  VT 
) const
inlineinherited

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 571 of file TargetLowering.h.

571  {
573  "Table isn't big enough!");
574  unsigned Ty = (unsigned)VT.SimpleTy;
575  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
576  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
assert(Globals.size() > 1)
bool llvm::TargetLoweringBase::getInsertFencesForAtomic ( ) const
inlineinherited

Return whether the DAG builder should automatically insert fences and reduce ordering for atomics.

Definition at line 889 of file TargetLowering.h.

889  {
890  return InsertFencesForAtomic;
891  }
unsigned llvm::TargetLoweringBase::getJumpBufAlignment ( ) const
inlineinherited

Returns the target's jmp_buf alignment in bytes (if never set, the default is 0)

Definition at line 863 of file TargetLowering.h.

863  {
864  return JumpBufAlignment;
865  }
unsigned JumpBufAlignment
The alignment, in bytes, of the target's jmp_buf buffers.
unsigned llvm::TargetLoweringBase::getJumpBufSize ( ) const
inlineinherited

Returns the target's jmp_buf size in bytes (if never set, the default is 200)

Definition at line 857 of file TargetLowering.h.

857  {
858  return JumpBufSize;
859  }
unsigned JumpBufSize
The size, in bytes, of the target's jmp_buf buffers.
unsigned ARMTargetLowering::getJumpTableEncoding ( ) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2293 of file ARMISelLowering.cpp.

CallingConv::ID llvm::TargetLoweringBase::getLibcallCallingConv ( RTLIB::Libcall  Call) const
inlineinherited

Get the CallingConv that should be used for the specified libcall.

Definition at line 1447 of file TargetLowering.h.

1447  {
1448  return LibcallCallingConvs[Call];
1449  }
CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]
Stores the CallingConv that should be used for each libcall.
const char* llvm::TargetLoweringBase::getLibcallName ( RTLIB::Libcall  Call) const
inlineinherited

Get the libcall routine name for the specified libcall.

Definition at line 1425 of file TargetLowering.h.

1425  {
1426  return LibcallRoutineNames[Call];
1427  }
const char * LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]
Stores the name each libcall.
LegalizeAction llvm::TargetLoweringBase::getLoadExtAction ( unsigned  ExtType,
MVT  VT 
) const
inlineinherited

Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 520 of file TargetLowering.h.

520  {
522  "Table isn't big enough!");
523  return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
524  }
assert(Globals.size() > 1)
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
unsigned ARMTargetLowering::getMaximalGlobalOffset ( ) const
overridevirtual

getMaximalGlobalOffset - Returns the maximal possible offset which can be used for loads / stores from the global.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1111 of file ARMISelLowering.cpp.

1111  {
1112  return (Subtarget->isThumb1Only() ? 127 : 4095);
1113 }
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
const ARMSubtarget * Subtarget
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemcpy ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memcpy.

This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 758 of file TargetLowering.h.

758  {
760  }
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemmove ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memmove.

This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 768 of file TargetLowering.h.

768  {
770  }
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemset ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memset.

This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 748 of file TargetLowering.h.

748  {
750  }
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned llvm::TargetLoweringBase::getMinFunctionAlignment ( ) const
inlineinherited

Return the minimum function alignment.

Definition at line 873 of file TargetLowering.h.

873  {
874  return MinFunctionAlignment;
875  }
int llvm::TargetLoweringBase::getMinimumJumpTableEntries ( ) const
inlineinherited

Return integer threshold on number of blocks to use jump tables rather than if sequence.

Definition at line 833 of file TargetLowering.h.

833  {
835  }
int MinimumJumpTableEntries
Number of blocks threshold to use jump tables.
unsigned llvm::TargetLoweringBase::getMinStackArgumentAlignment ( ) const
inlineinherited

Return the minimum stack alignment of an argument.

Definition at line 868 of file TargetLowering.h.

868  {
870  }
unsigned MinStackArgumentAlignment
The minimum alignment that any argument on the stack needs to have.
TargetLowering::ConstraintWeight TargetLowering::getMultipleConstraintMatchWeight ( AsmOperandInfo info,
int  maIndex 
) const
virtualinherited

Examine constraint type and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Definition at line 2442 of file TargetLowering.cpp.

2443  {
2445  if (maIndex >= (int)info.multipleAlternatives.size())
2446  rCodes = &info.Codes;
2447  else
2448  rCodes = &info.multipleAlternatives[maIndex].Codes;
2449  ConstraintWeight BestWeight = CW_Invalid;
2450 
2451  // Loop over the options, keeping track of the most general one.
2452  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2453  ConstraintWeight weight =
2454  getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2455  if (weight > BestWeight)
2456  BestWeight = weight;
2457  }
2458 
2459  return BestWeight;
2460 }
lazy value info
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
std::vector< std::string > ConstraintCodeVector
Definition: InlineAsm.h:102
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
unsigned llvm::TargetLoweringBase::getNumRegisters ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Return the number of registers that this ValueType will eventually require.

This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.

Definition at line 703 of file TargetLowering.h.

703  {
704  if (VT.isSimple()) {
705  assert((unsigned)VT.getSimpleVT().SimpleTy <
707  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
708  }
709  if (VT.isVector()) {
710  EVT VT1;
711  MVT VT2;
712  unsigned NumIntermediates;
713  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
714  }
715  if (VT.isInteger()) {
716  unsigned BitWidth = VT.getSizeInBits();
717  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
718  return (BitWidth + RegWidth - 1) / RegWidth;
719  }
720  llvm_unreachable("Unsupported extended type!");
721  }
unsigned getSizeInBits() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
const TargetLoweringObjectFile& llvm::TargetLoweringBase::getObjFileLowering ( ) const
inlineinherited

Definition at line 151 of file TargetLowering.h.

151 { return TLOF; }
const TargetLoweringObjectFile & TLOF
True if this is a little endian target.
LegalizeAction llvm::TargetLoweringBase::getOperationAction ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 477 of file TargetLowering.h.

477  {
478  if (VT.isExtended()) return Expand;
479  // If a target-specific SDNode requires legalization, require the target
480  // to provide custom legalization for it.
481  if (Op > array_lengthof(OpActions[0])) return Custom;
482  unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
483  return (LegalizeAction)OpActions[I][Op];
484  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
#define I(x, y, z)
Definition: MD5.cpp:54
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
EVT ARMTargetLowering::getOptimalMemOpType ( uint64_t  Size,
unsigned  DstAlign,
unsigned  SrcAlign,
bool  IsMemset,
bool  ZeroMemset,
bool  MemcpyStrSrc,
MachineFunction MF 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9739 of file ARMISelLowering.cpp.

9743  {
9744  const Function *F = MF.getFunction();
9745 
9746  // See if we can use NEON instructions for this...
9747  if ((!IsMemset || ZeroMemset) &&
9748  Subtarget->hasNEON() &&
9751  bool Fast;
9752  if (Size >= 16 &&
9753  (memOpAlign(SrcAlign, DstAlign, 16) ||
9754  (allowsUnalignedMemoryAccesses(MVT::v2f64, 0, &Fast) && Fast))) {
9755  return MVT::v2f64;
9756  } else if (Size >= 8 &&
9757  (memOpAlign(SrcAlign, DstAlign, 8) ||
9758  (allowsUnalignedMemoryAccesses(MVT::f64, 0, &Fast) && Fast))) {
9759  return MVT::f64;
9760  }
9761  }
9762 
9763  // Lowering to i32/i16 if the size permits.
9764  if (Size >= 4)
9765  return MVT::i32;
9766  else if (Size >= 2)
9767  return MVT::i16;
9768 
9769  // Let the target-independent logic figure it out.
9770  return MVT::Other;
9771 }
F(f)
const Function * getFunction() const
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace, bool *Fast) const override
bool hasNEON() const
Definition: ARMSubtarget.h:311
const ARMSubtarget * Subtarget
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
Disable implicit floating point insts.
Definition: Attributes.h:86
static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign, unsigned AlignCheck)
SDValue TargetLowering::getPICJumpTableRelocBase ( SDValue  Table,
SelectionDAG DAG 
) const
virtualinherited

Returns relocation base for the given PIC jumptable.

Reimplemented in llvm::X86TargetLowering.

Definition at line 235 of file TargetLowering.cpp.

236  {
237  // If our PIC model is GP relative, use the global offset table as the base.
238  unsigned JTEncoding = getJumpTableEncoding();
239 
240  if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
242  return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
243 
244  return Table;
245 }
virtual MVT getPointerTy(uint32_t=0) const
virtual unsigned getJumpTableEncoding() const
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Definition: SelectionDAG.h:631
const MCExpr * TargetLowering::getPICJumpTableRelocBaseExpr ( const MachineFunction MF,
unsigned  JTI,
MCContext Ctx 
) const
virtualinherited

This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

getPICJumpTableRelocBaseExpr - This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

Reimplemented in llvm::X86TargetLowering.

Definition at line 251 of file TargetLowering.cpp.

252  {
253  // The normal PIC reloc base is the label at the start of the jump table.
254  return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
255 }
static const MCSymbolRefExpr * Create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:293
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
unsigned TargetLoweringBase::getPointerSizeInBits ( uint32_t  AS = 0) const
inherited

Definition at line 847 of file TargetLoweringBase.cpp.

847  {
848  return DL->getPointerSizeInBits(AS);
849 }
const DataLayout * DL
True if this is a little endian target.
unsigned getPointerSizeInBits(unsigned AS=0) const
Definition: DataLayout.h:313
MVT TargetLoweringBase::getPointerTy ( uint32_t  AS = 0) const
virtualinherited

Return the pointer type for the given address space, defaults to the pointer type from the data layout. FIXME: The default needs to be removed once all the code is updated.

Definition at line 843 of file TargetLoweringBase.cpp.

843  {
845 }
static MVT getIntegerVT(unsigned BitWidth)
unsigned getPointerSizeInBits(uint32_t AS=0) const
unsigned TargetLoweringBase::getPointerTypeSizeInBits ( Type Ty) const
inherited

Definition at line 851 of file TargetLoweringBase.cpp.

851  {
852  assert(Ty->isPointerTy());
854 }
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: Type.cpp:212
unsigned getPointerSizeInBits(uint32_t AS=0) const
assert(Globals.size() > 1)
bool isPointerTy() const
Definition: Type.h:217
bool ARMTargetLowering::getPostIndexedAddressParts ( SDNode N,
SDNode Op,
SDValue Base,
SDValue Offset,
ISD::MemIndexedMode AM,
SelectionDAG DAG 
) const
overridevirtual

getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

Reimplemented from llvm::TargetLowering.

Definition at line 10155 of file ARMISelLowering.cpp.

10159  {
10160  if (Subtarget->isThumb1Only())
10161  return false;
10162 
10163  EVT VT;
10164  SDValue Ptr;
10165  bool isSEXTLoad = false;
10166  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10167  VT = LD->getMemoryVT();
10168  Ptr = LD->getBasePtr();
10169  isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10170  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10171  VT = ST->getMemoryVT();
10172  Ptr = ST->getBasePtr();
10173  } else
10174  return false;
10175 
10176  bool isInc;
10177  bool isLegal = false;
10178  if (Subtarget->isThumb2())
10179  isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10180  isInc, DAG);
10181  else
10182  isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10183  isInc, DAG);
10184  if (!isLegal)
10185  return false;
10186 
10187  if (Ptr != Base) {
10188  // Swap base ptr and offset to catch more post-index load / store when
10189  // it's legal. In Thumb2 mode, offset must be an immediate.
10190  if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10191  !Subtarget->isThumb2())
10192  std::swap(Base, Offset);
10193 
10194  // Post-indexed load / store update the base pointer.
10195  if (Ptr != Base)
10196  return false;
10197  }
10198 
10199  AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10200  return true;
10201 }
unsigned getOpcode() const
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
bool isSEXTLoad(const SDNode *N)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
const ARMSubtarget * Subtarget
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
bool isThumb2() const
Definition: ARMSubtarget.h:402
static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
virtual TargetLoweringBase::LegalizeTypeAction llvm::TargetLoweringBase::getPreferredVectorAction ( EVT  VT) const
inlinevirtualinherited

Return the preferred vector type legalization action.

Reimplemented in llvm::X86TargetLowering, llvm::NVPTXTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 190 of file TargetLowering.h.

190  {
191  // The default action for one element vectors is to scalarize
192  if (VT.getVectorNumElements() == 1)
193  return TypeScalarizeVector;
194  // The default action for other vectors is to promote
195  return TypePromoteInteger;
196  }
unsigned llvm::TargetLoweringBase::getPrefFunctionAlignment ( ) const
inlineinherited

Return the preferred function alignment.

Definition at line 878 of file TargetLowering.h.

878  {
879  return PrefFunctionAlignment;
880  }
unsigned llvm::TargetLoweringBase::getPrefLoopAlignment ( ) const
inlineinherited

Return the preferred loop alignment.

Definition at line 883 of file TargetLowering.h.

883  {
884  return PrefLoopAlignment;
885  }
unsigned PrefLoopAlignment
The preferred loop alignment.
bool ARMTargetLowering::getPreIndexedAddressParts ( SDNode N,
SDValue Base,
SDValue Offset,
ISD::MemIndexedMode AM,
SelectionDAG DAG 
) const
overridevirtual

getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

Reimplemented from llvm::TargetLowering.

Definition at line 10117 of file ARMISelLowering.cpp.

10120  {
10121  if (Subtarget->isThumb1Only())
10122  return false;
10123 
10124  EVT VT;
10125  SDValue Ptr;
10126  bool isSEXTLoad = false;
10127  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10128  Ptr = LD->getBasePtr();
10129  VT = LD->getMemoryVT();
10130  isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10131  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10132  Ptr = ST->getBasePtr();
10133  VT = ST->getMemoryVT();
10134  } else
10135  return false;
10136 
10137  bool isInc;
10138  bool isLegal = false;
10139  if (Subtarget->isThumb2())
10140  isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10141  Offset, isInc, DAG);
10142  else
10143  isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10144  Offset, isInc, DAG);
10145  if (!isLegal)
10146  return false;
10147 
10148  AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10149  return true;
10150 }
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
bool isSEXTLoad(const SDNode *N)
SDNode * getNode() const
get the SDNode which holds the desired result
static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
const ARMSubtarget * Subtarget
bool isThumb2() const
Definition: ARMSubtarget.h:402
static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
const TargetRegisterClass * ARMTargetLowering::getRegClassFor ( MVT  VT) const
overridevirtual

getRegClassFor - Return the register class that should be used for the specified value type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1089 of file ARMISelLowering.cpp.

1089  {
1090  // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1091  // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1092  // load / store 4 to 8 consecutive D registers.
1093  if (Subtarget->hasNEON()) {
1094  if (VT == MVT::v4i64)
1095  return &ARM::QQPRRegClass;
1096  if (VT == MVT::v8i64)
1097  return &ARM::QQQQPRRegClass;
1098  }
1099  return TargetLowering::getRegClassFor(VT);
1100 }
bool hasNEON() const
Definition: ARMSubtarget.h:311
const ARMSubtarget * Subtarget
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
RCPair ARMTargetLowering::getRegForInlineAsmConstraint ( const std::string &  Constraint,
MVT  VT 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 10347 of file ARMISelLowering.cpp.

10348  {
10349  if (Constraint.size() == 1) {
10350  // GCC ARM Constraint Letters
10351  switch (Constraint[0]) {
10352  case 'l': // Low regs or general regs.
10353  if (Subtarget->isThumb())
10354  return RCPair(0U, &ARM::tGPRRegClass);
10355  return RCPair(0U, &ARM::GPRRegClass);
10356  case 'h': // High regs or no regs.
10357  if (Subtarget->isThumb())
10358  return RCPair(0U, &ARM::hGPRRegClass);
10359  break;
10360  case 'r':
10361  return RCPair(0U, &ARM::GPRRegClass);
10362  case 'w':
10363  if (VT == MVT::Other)
10364  break;
10365  if (VT == MVT::f32)
10366  return RCPair(0U, &ARM::SPRRegClass);
10367  if (VT.getSizeInBits() == 64)
10368  return RCPair(0U, &ARM::DPRRegClass);
10369  if (VT.getSizeInBits() == 128)
10370  return RCPair(0U, &ARM::QPRRegClass);
10371  break;
10372  case 'x':
10373  if (VT == MVT::Other)
10374  break;
10375  if (VT == MVT::f32)
10376  return RCPair(0U, &ARM::SPR_8RegClass);
10377  if (VT.getSizeInBits() == 64)
10378  return RCPair(0U, &ARM::DPR_8RegClass);
10379  if (VT.getSizeInBits() == 128)
10380  return RCPair(0U, &ARM::QPR_8RegClass);
10381  break;
10382  case 't':
10383  if (VT == MVT::f32)
10384  return RCPair(0U, &ARM::SPRRegClass);
10385  break;
10386  }
10387  }
10388  if (StringRef("{cc}").equals_lower(Constraint))
10389  return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10390 
10391  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10392 }
unsigned getSizeInBits() const
bool isThumb() const
Definition: ARMSubtarget.h:400
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
std::pair< unsigned, const TargetRegisterClass * > RCPair
const ARMSubtarget * Subtarget
unsigned ARMTargetLowering::getRegisterByName ( const char *  RegName,
EVT  VT 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 3941 of file ARMISelLowering.cpp.

3942  {
3943  unsigned Reg = StringSwitch<unsigned>(RegName)
3944  .Case("sp", ARM::SP)
3945  .Default(0);
3946  if (Reg)
3947  return Reg;
3948  report_fatal_error("Invalid register name global variable");
3949 }
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Reg
All possible values of the reg field in the ModR/M byte.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
R Default(const T &Value) const
Definition: StringSwitch.h:111
MVT llvm::TargetLoweringBase::getRegisterType ( MVT  VT) const
inlineinherited

Return the type of registers that this ValueType will eventually require.

Definition at line 669 of file TargetLowering.h.

669  {
670  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
671  return RegisterTypeForVT[VT.SimpleTy];
672  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
MVT llvm::TargetLoweringBase::getRegisterType ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Return the type of registers that this ValueType will eventually require.

Definition at line 675 of file TargetLowering.h.

675  {
676  if (VT.isSimple()) {
677  assert((unsigned)VT.getSimpleVT().SimpleTy <
679  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
680  }
681  if (VT.isVector()) {
682  EVT VT1;
683  MVT RegisterVT;
684  unsigned NumIntermediates;
685  (void)getVectorTypeBreakdown(Context, VT, VT1,
686  NumIntermediates, RegisterVT);
687  return RegisterVT;
688  }
689  if (VT.isInteger()) {
690  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
691  }
692  llvm_unreachable("Unsupported extended type!");
693  }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
virtual uint8_t llvm::TargetLoweringBase::getRepRegClassCostFor ( MVT  VT) const
inlinevirtualinherited

Return the cost of the 'representative' register class for the specified value type.

Definition at line 334 of file TargetLowering.h.

334  {
335  return RepRegClassCostForVT[VT.SimpleTy];
336  }
uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]
virtual const TargetRegisterClass* llvm::TargetLoweringBase::getRepRegClassFor ( MVT  VT) const
inlinevirtualinherited

Return the 'representative' register class for the specified value type.

The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.

Reimplemented in llvm::MipsSETargetLowering.

Definition at line 327 of file TargetLowering.h.

327  {
328  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
329  return RC;
330  }
const TargetRegisterClass * RepRegClassForVT[MVT::LAST_VALUETYPE]
MVT TargetLoweringBase::getScalarShiftAmountTy ( EVT  LHSTy) const
virtualinherited
virtual int llvm::TargetLoweringBase::getScalingFactorCost ( const AddrMode AM,
Type Ty 
) const
inlinevirtualinherited

Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type.

If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. TODO: Handle pre/postinc as well.

Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.

Definition at line 1271 of file TargetLowering.h.

1271  {
1272  // Default: assume that any scaling factor used in a legal AM is free.
1273  if (isLegalAddressingMode(AM, Ty)) return 0;
1274  return -1;
1275  }
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( ) const
inlineinherited

Return target scheduling preference.

Definition at line 301 of file TargetLowering.h.

301  {
302  return SchedPreferenceInfo;
303  }
Sched::Preference SchedPreferenceInfo
Sched::Preference ARMTargetLowering::getSchedulingPreference ( SDNode N) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1115 of file ARMISelLowering.cpp.

1115  {
1116  unsigned NumVals = N->getNumValues();
1117  if (!NumVals)
1118  return Sched::RegPressure;
1119 
1120  for (unsigned i = 0; i != NumVals; ++i) {
1121  EVT VT = N->getValueType(i);
1122  if (VT == MVT::Glue || VT == MVT::Other)
1123  continue;
1124  if (VT.isFloatingPoint() || VT.isVector())
1125  return Sched::ILP;
1126  }
1127 
1128  if (!N->isMachineOpcode())
1129  return Sched::RegPressure;
1130 
1131  // Load are scheduled for latency even if there instruction itinerary
1132  // is not available.
1134  const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1135 
1136  if (MCID.getNumDefs() == 0)
1137  return Sched::RegPressure;
1138  if (!Itins->isEmpty() &&
1139  Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1140  return Sched::ILP;
1141 
1142  return Sched::RegPressure;
1143 }
const TargetMachine & getTargetMachine() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions. Register definitions always occur...
Definition: MCInstrDesc.h:198
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
const HexagonInstrInfo * TII
EVT getValueType(unsigned ResNo) const
const InstrItineraryData * Itins
unsigned getNumValues() const
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
virtual const TargetInstrInfo * getInstrInfo() const
unsigned getSchedClass() const
Return the scheduling class for this instruction. The scheduling class is an index into the InstrItin...
Definition: MCInstrDesc.h:570
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
bool isMachineOpcode() const
unsigned getMachineOpcode() const
virtual const MCPhysReg* llvm::TargetLowering::getScratchRegisters ( CallingConv::ID  CC) const
inlinevirtualinherited

Returns a 0 terminated array of registers that can be safely used as scratch registers.

Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.

Definition at line 2344 of file TargetLowering.h.

2344  {
2345  return nullptr;
2346  }
EVT ARMTargetLowering::getSetCCResultType ( LLVMContext Context,
EVT  VT 
) const
overridevirtual

getSetCCResultType - Return the value type to use for ISD::SETCC.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1082 of file ARMISelLowering.cpp.

1082  {
1083  if (!VT.isVector()) return getPointerTy();
1085 }
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
virtual MVT getPointerTy(uint32_t=0) const
EVT changeVectorElementTypeToInteger() const
Definition: ValueTypes.h:81
EVT TargetLoweringBase::getShiftAmountTy ( EVT  LHSTy) const
inherited

Definition at line 860 of file TargetLoweringBase.cpp.

860  {
861  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
862  if (LHSTy.isVector())
863  return LHSTy;
864  return getScalarShiftAmountTy(LHSTy);
865 }
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
assert(Globals.size() > 1)
MVT llvm::TargetLoweringBase::getSimpleValueType ( Type Ty,
bool  AllowUnknown = false 
) const
inlineinherited

Return the MVT corresponding to this LLVM type. See getValueType.

Definition at line 659 of file TargetLowering.h.

659  {
660  return getValueType(Ty, AllowUnknown).getSimpleVT();
661  }
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
MVT getSimpleVT() const
Definition: ValueTypes.h:204
TargetLowering::ConstraintWeight ARMTargetLowering::getSingleConstraintMatchWeight ( AsmOperandInfo info,
const char *  constraint 
) const
overridevirtual

Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Reimplemented from llvm::TargetLowering.

Definition at line 10315 of file ARMISelLowering.cpp.

10316  {
10317  ConstraintWeight weight = CW_Invalid;
10318  Value *CallOperandVal = info.CallOperandVal;
10319  // If we don't have a value, we can't do a match,
10320  // but allow it at the lowest weight.
10321  if (!CallOperandVal)
10322  return CW_Default;
10323  Type *type = CallOperandVal->getType();
10324  // Look at the constraint type.
10325  switch (*constraint) {
10326  default:
10328  break;
10329  case 'l':
10330  if (type->isIntegerTy()) {
10331  if (Subtarget->isThumb())
10332  weight = CW_SpecificReg;
10333  else
10334  weight = CW_Register;
10335  }
10336  break;
10337  case 'w':
10338  if (type->isFloatingPointTy())
10339  weight = CW_Register;
10340  break;
10341  }
10342  return weight;
10343 }
lazy value info
bool isThumb() const
Definition: ARMSubtarget.h:400
bool isFloatingPointTy() const
Definition: Type.h:159
Type * getType() const
Definition: Value.h:215
const ARMSubtarget * Subtarget
bool isIntegerTy() const
Definition: Type.h:193
LLVM Value Representation.
Definition: Value.h:69
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
virtual bool llvm::TargetLoweringBase::getStackCookieLocation ( unsigned &  ,
unsigned &   
) const
inlinevirtualinherited

Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate.

Reimplemented in llvm::X86TargetLowering.

Definition at line 896 of file TargetLowering.h.

897  {
898  return false;
899  }
unsigned llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore ( ) const
inlineinherited

If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 839 of file TargetLowering.h.

839  {
841  }
unsigned StackPointerRegisterToSaveRestore
const ARMSubtarget* llvm::ARMTargetLowering::getSubtarget ( ) const
inline

Definition at line 346 of file ARMISelLowering.h.

346  {
347  return Subtarget;
348  }
const ARMSubtarget * Subtarget
const TargetMachine& llvm::TargetLoweringBase::getTargetMachine ( ) const
inlineinherited

Definition at line 149 of file TargetLowering.h.

149 { return TM; }
const TargetMachine & TM
True if this is a little endian target.
const char * ARMTargetLowering::getTargetNodeName ( unsigned  Opcode) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 943 of file ARMISelLowering.cpp.

943  {
944  switch (Opcode) {
945  default: return nullptr;
946  case ARMISD::Wrapper: return "ARMISD::Wrapper";
947  case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
948  case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
949  case ARMISD::CALL: return "ARMISD::CALL";
950  case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
951  case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
952  case ARMISD::tCALL: return "ARMISD::tCALL";
953  case ARMISD::BRCOND: return "ARMISD::BRCOND";
954  case ARMISD::BR_JT: return "ARMISD::BR_JT";
955  case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
956  case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
957  case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
958  case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
959  case ARMISD::CMP: return "ARMISD::CMP";
960  case ARMISD::CMN: return "ARMISD::CMN";
961  case ARMISD::CMPZ: return "ARMISD::CMPZ";
962  case ARMISD::CMPFP: return "ARMISD::CMPFP";
963  case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
964  case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
965  case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
966 
967  case ARMISD::CMOV: return "ARMISD::CMOV";
968 
969  case ARMISD::RBIT: return "ARMISD::RBIT";
970 
971  case ARMISD::FTOSI: return "ARMISD::FTOSI";
972  case ARMISD::FTOUI: return "ARMISD::FTOUI";
973  case ARMISD::SITOF: return "ARMISD::SITOF";
974  case ARMISD::UITOF: return "ARMISD::UITOF";
975 
976  case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
977  case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
978  case ARMISD::RRX: return "ARMISD::RRX";
979 
980  case ARMISD::ADDC: return "ARMISD::ADDC";
981  case ARMISD::ADDE: return "ARMISD::ADDE";
982  case ARMISD::SUBC: return "ARMISD::SUBC";
983  case ARMISD::SUBE: return "ARMISD::SUBE";
984 
985  case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
986  case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
987 
988  case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
989  case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
990 
991  case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
992 
993  case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
994 
995  case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
996 
997  case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
998 
999  case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1000 
1001  case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1002 
1003  case ARMISD::VCEQ: return "ARMISD::VCEQ";
1004  case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1005  case ARMISD::VCGE: return "ARMISD::VCGE";
1006  case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1007  case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1008  case ARMISD::VCGEU: return "ARMISD::VCGEU";
1009  case ARMISD::VCGT: return "ARMISD::VCGT";
1010  case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1011  case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1012  case ARMISD::VCGTU: return "ARMISD::VCGTU";
1013  case ARMISD::VTST: return "ARMISD::VTST";
1014 
1015  case ARMISD::VSHL: return "ARMISD::VSHL";
1016  case ARMISD::VSHRs: return "ARMISD::VSHRs";
1017  case ARMISD::VSHRu: return "ARMISD::VSHRu";
1018  case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1019  case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1020  case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1021  case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1022  case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1023  case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1024  case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1025  case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1026  case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1027  case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1028  case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1029  case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1030  case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1031  case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1032  case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1033  case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1034  case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1035  case ARMISD::VDUP: return "ARMISD::VDUP";
1036  case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1037  case ARMISD::VEXT: return "ARMISD::VEXT";
1038  case ARMISD::VREV64: return "ARMISD::VREV64";
1039  case ARMISD::VREV32: return "ARMISD::VREV32";
1040  case ARMISD::VREV16: return "ARMISD::VREV16";
1041  case ARMISD::VZIP: return "ARMISD::VZIP";
1042  case ARMISD::VUZP: return "ARMISD::VUZP";
1043  case ARMISD::VTRN: return "ARMISD::VTRN";
1044  case ARMISD::VTBL1: return "ARMISD::VTBL1";
1045  case ARMISD::VTBL2: return "ARMISD::VTBL2";
1046  case ARMISD::VMULLs: return "ARMISD::VMULLs";
1047  case ARMISD::VMULLu: return "ARMISD::VMULLu";
1048  case ARMISD::UMLAL: return "ARMISD::UMLAL";
1049  case ARMISD::SMLAL: return "ARMISD::SMLAL";
1050  case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1051  case ARMISD::FMAX: return "ARMISD::FMAX";
1052  case ARMISD::FMIN: return "ARMISD::FMIN";
1053  case ARMISD::VMAXNM: return "ARMISD::VMAX";
1054  case ARMISD::VMINNM: return "ARMISD::VMIN";
1055  case ARMISD::BFI: return "ARMISD::BFI";
1056  case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1057  case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1058  case ARMISD::VBSL: return "ARMISD::VBSL";
1059  case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1060  case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1061  case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1062  case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1063  case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1064  case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1065  case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1066  case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1067  case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1068  case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1069  case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1070  case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1071  case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1072  case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1073  case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1074  case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1075  case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1076  case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1077  case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1078  case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1079  }
1080 }
bool ARMTargetLowering::getTgtMemIntrinsic ( IntrinsicInfo Info,
const CallInst I,
unsigned  Intrinsic 
) const
overridevirtual

getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes. The associated MachineMemOperands record the alignment specified in the intrinsic calls.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10669 of file ARMISelLowering.cpp.

10671  {
10672  switch (Intrinsic) {
10673  case Intrinsic::arm_neon_vld1:
10674  case Intrinsic::arm_neon_vld2:
10675  case Intrinsic::arm_neon_vld3:
10676  case Intrinsic::arm_neon_vld4:
10677  case Intrinsic::arm_neon_vld2lane:
10678  case Intrinsic::arm_neon_vld3lane:
10679  case Intrinsic::arm_neon_vld4lane: {
10680  Info.opc = ISD::INTRINSIC_W_CHAIN;
10681  // Conservatively set memVT to the entire set of vectors loaded.
10682  uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
10683  Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10684  Info.ptrVal = I.getArgOperand(0);
10685  Info.offset = 0;
10686  Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10687  Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10688  Info.vol = false; // volatile loads with NEON intrinsics not supported
10689  Info.readMem = true;
10690  Info.writeMem = false;
10691  return true;
10692  }
10693  case Intrinsic::arm_neon_vst1:
10694  case Intrinsic::arm_neon_vst2:
10695  case Intrinsic::arm_neon_vst3:
10696  case Intrinsic::arm_neon_vst4:
10697  case Intrinsic::arm_neon_vst2lane:
10698  case Intrinsic::arm_neon_vst3lane:
10699  case Intrinsic::arm_neon_vst4lane: {
10700  Info.opc = ISD::INTRINSIC_VOID;
10701  // Conservatively set memVT to the entire set of vectors stored.
10702  unsigned NumElts = 0;
10703  for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
10704  Type *ArgTy = I.getArgOperand(ArgI)->getType();
10705  if (!ArgTy->isVectorTy())
10706  break;
10707  NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
10708  }
10709  Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10710  Info.ptrVal = I.getArgOperand(0);
10711  Info.offset = 0;
10712  Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10713  Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10714  Info.vol = false; // volatile stores with NEON intrinsics not supported
10715  Info.readMem = false;
10716  Info.writeMem = true;
10717  return true;
10718  }
10719  case Intrinsic::arm_ldaex:
10720  case Intrinsic::arm_ldrex: {
10721  PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
10722  Info.opc = ISD::INTRINSIC_W_CHAIN;
10723  Info.memVT = MVT::getVT(PtrTy->getElementType());
10724  Info.ptrVal = I.getArgOperand(0);
10725  Info.offset = 0;
10726  Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10727  Info.vol = true;
10728  Info.readMem = true;
10729  Info.writeMem = false;
10730  return true;
10731  }
10732  case Intrinsic::arm_stlex:
10733  case Intrinsic::arm_strex: {
10734  PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
10735  Info.opc = ISD::INTRINSIC_W_CHAIN;
10736  Info.memVT = MVT::getVT(PtrTy->getElementType());
10737  Info.ptrVal = I.getArgOperand(1);
10738  Info.offset = 0;
10739  Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10740  Info.vol = true;
10741  Info.readMem = false;
10742  Info.writeMem = true;
10743  return true;
10744  }
10745  case Intrinsic::arm_stlexd:
10746  case Intrinsic::arm_strexd: {
10747  Info.opc = ISD::INTRINSIC_W_CHAIN;
10748  Info.memVT = MVT::i64;
10749  Info.ptrVal = I.getArgOperand(2);
10750  Info.offset = 0;
10751  Info.align = 8;
10752  Info.vol = true;
10753  Info.readMem = false;
10754  Info.writeMem = true;
10755  return true;
10756  }
10757  case Intrinsic::arm_ldaexd:
10758  case Intrinsic::arm_ldrexd: {
10759  Info.opc = ISD::INTRINSIC_W_CHAIN;
10760  Info.memVT = MVT::i64;
10761  Info.ptrVal = I.getArgOperand(0);
10762  Info.offset = 0;
10763  Info.align = 8;
10764  Info.vol = true;
10765  Info.readMem = true;
10766  Info.writeMem = false;
10767  return true;
10768  }
10769  default:
10770  break;
10771  }
10772 
10773  return false;
10774 }
unsigned getNumArgOperands() const
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
Type * getElementType() const
Definition: DerivedTypes.h:319
bool isVectorTy() const
Definition: Type.h:226
const DataLayout * getDataLayout() const
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:247
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
unsigned getABITypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:683
uint64_t getTypeAllocSize(Type *Ty) const
Definition: DataLayout.h:368
Type * getType() const
Definition: Value.h:215
Value * getArgOperand(unsigned i) const
LLVM Value Representation.
Definition: Value.h:69
LegalizeAction llvm::TargetLoweringBase::getTruncStoreAction ( MVT  ValVT,
MVT  MemVT 
) const
inlineinherited

Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 535 of file TargetLowering.h.

535  {
536  assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
537  "Table isn't big enough!");
538  return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
539  [MemVT.SimpleTy];
540  }
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
assert(Globals.size() > 1)
LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.

Definition at line 375 of file TargetLowering.h.

375  {
376  return getTypeConversion(Context, VT).first;
377  }
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( MVT  VT) const
inlineinherited

Definition at line 378 of file TargetLowering.h.

378  {
379  return ValueTypeActions.getTypeAction(VT);
380  }
LegalizeTypeAction getTypeAction(MVT VT) const
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
LegalizeKind llvm::TargetLoweringBase::getTypeConversion ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Reset the operation actions based on target options.

Definition at line 1629 of file TargetLowering.h.

1629  {
1630  // If this is a simple type, use the ComputeRegisterProp mechanism.
1631  if (VT.isSimple()) {
1632  MVT SVT = VT.getSimpleVT();
1633  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1634  MVT NVT = TransformToType[SVT.SimpleTy];
1636 
1637  assert(
1638  (LA == TypeLegal || LA == TypeSoftenFloat ||
1640  && "Promote may not follow Expand or Promote");
1641 
1642  if (LA == TypeSplitVector)
1643  return LegalizeKind(LA, EVT::getVectorVT(Context,
1644  SVT.getVectorElementType(),
1645  SVT.getVectorNumElements()/2));
1646  if (LA == TypeScalarizeVector)
1647  return LegalizeKind(LA, SVT.getVectorElementType());
1648  return LegalizeKind(LA, NVT);
1649  }
1650 
1651  // Handle Extended Scalar Types.
1652  if (!VT.isVector()) {
1653  assert(VT.isInteger() && "Float types must be simple");
1654  unsigned BitSize = VT.getSizeInBits();
1655  // First promote to a power-of-two size, then expand if necessary.
1656  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1657  EVT NVT = VT.getRoundIntegerType(Context);
1658  assert(NVT != VT && "Unable to round integer VT");
1659  LegalizeKind NextStep = getTypeConversion(Context, NVT);
1660  // Avoid multi-step promotion.
1661  if (NextStep.first == TypePromoteInteger) return NextStep;
1662  // Return rounded integer type.
1663  return LegalizeKind(TypePromoteInteger, NVT);
1664  }
1665 
1667  EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1668  }
1669 
1670  // Handle vector types.
1671  unsigned NumElts = VT.getVectorNumElements();
1672  EVT EltVT = VT.getVectorElementType();
1673 
1674  // Vectors with only one element are always scalarized.
1675  if (NumElts == 1)
1676  return LegalizeKind(TypeScalarizeVector, EltVT);
1677 
1678  // Try to widen vector elements until the element type is a power of two and
1679  // promote it to a legal type later on, for example:
1680  // <3 x i8> -> <4 x i8> -> <4 x i32>
1681  if (EltVT.isInteger()) {
1682  // Vectors with a number of elements that is not a power of two are always
1683  // widened, for example <3 x i8> -> <4 x i8>.
1684  if (!VT.isPow2VectorType()) {
1685  NumElts = (unsigned)NextPowerOf2(NumElts);
1686  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1687  return LegalizeKind(TypeWidenVector, NVT);
1688  }
1689 
1690  // Examine the element type.
1691  LegalizeKind LK = getTypeConversion(Context, EltVT);
1692 
1693  // If type is to be expanded, split the vector.
1694  // <4 x i140> -> <2 x i140>
1695  if (LK.first == TypeExpandInteger)
1697  EVT::getVectorVT(Context, EltVT, NumElts / 2));
1698 
1699  // Promote the integer element types until a legal vector type is found
1700  // or until the element integer type is too big. If a legal type was not
1701  // found, fallback to the usual mechanism of widening/splitting the
1702  // vector.
1703  EVT OldEltVT = EltVT;
1704  while (1) {
1705  // Increase the bitwidth of the element to the next pow-of-two
1706  // (which is greater than 8 bits).
1707  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1708  ).getRoundIntegerType(Context);
1709 
1710  // Stop trying when getting a non-simple element type.
1711  // Note that vector elements may be greater than legal vector element
1712  // types. Example: X86 XMM registers hold 64bit element on 32bit
1713  // systems.
1714  if (!EltVT.isSimple()) break;
1715 
1716  // Build a new vector type and check if it is legal.
1717  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1718  // Found a legal promoted vector type.
1719  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1721  EVT::getVectorVT(Context, EltVT, NumElts));
1722  }
1723 
1724  // Reset the type to the unexpanded type if we did not find a legal vector
1725  // type with a promoted vector element type.
1726  EltVT = OldEltVT;
1727  }
1728 
1729  // Try to widen the vector until a legal type is found.
1730  // If there is no wider legal type, split the vector.
1731  while (1) {
1732  // Round up to the next power of 2.
1733  NumElts = (unsigned)NextPowerOf2(NumElts);
1734 
1735  // If there is no simple vector type with this many elements then there
1736  // cannot be a larger legal vector type. Note that this assumes that
1737  // there are no skipped intermediate vector types in the simple types.
1738  if (!EltVT.isSimple()) break;
1739  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1740  if (LargerVector == MVT()) break;
1741 
1742  // If this type is legal then widen the vector.
1743  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1744  return LegalizeKind(TypeWidenVector, LargerVector);
1745  }
1746 
1747  // Widen odd vectors to next power of two.
1748  if (!VT.isPow2VectorType()) {
1749  EVT NVT = VT.getPow2VectorType(Context);
1750  return LegalizeKind(TypeWidenVector, NVT);
1751  }
1752 
1753  // Vectors with illegal element types are expanded.
1754  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1755  return LegalizeKind(TypeSplitVector, NVT);
1756  }
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT TransformToType[MVT::LAST_VALUETYPE]
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
LegalizeTypeAction getTypeAction(MVT VT) const
uint64_t NextPowerOf2(uint64_t A)
Definition: MathExtras.h:567
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
virtual MVT llvm::TargetLowering::getTypeForExtArgOrReturn ( MVT  VT,
ISD::NodeType   
) const
inlinevirtualinherited

Return the type that should be used to zero or sign extend a zeroext/signext integer argument or return value. FIXME: Most C calling convention requires the return type to be promoted, but this is not true all the time, e.g. i1 on x86-64. It is also not necessary for non-C calling conventions. The frontend should handle this and include all of the necessary information.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2327 of file TargetLowering.h.

2328  {
2329  MVT MinVT = getRegisterType(MVT::i32);
2330  return VT.bitsLT(MinVT) ? MinVT : VT;
2331  }
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
std::pair< unsigned, MVT > TargetLoweringBase::getTypeLegalizationCost ( Type Ty) const
inherited

Estimate the cost of type-legalization and the legalized type.

Definition at line 1425 of file TargetLoweringBase.cpp.

1425  {
1426  LLVMContext &C = Ty->getContext();
1427  EVT MTy = getValueType(Ty);
1428 
1429  unsigned Cost = 1;
1430  // We keep legalizing the type until we find a legal kind. We assume that
1431  // the only operation that costs anything is the split. After splitting
1432  // we need to handle two types.
1433  while (true) {
1434  LegalizeKind LK = getTypeConversion(C, MTy);
1435 
1436  if (LK.first == TypeLegal)
1437  return std::make_pair(Cost, MTy.getSimpleVT());
1438 
1439  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1440  Cost *= 2;
1441 
1442  // Keep legalizing the type.
1443  MTy = LK.second;
1444  }
1445 }
std::pair< LegalizeTypeAction, EVT > LegalizeKind
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
MVT getSimpleVT() const
Definition: ValueTypes.h:204
EVT llvm::TargetLoweringBase::getTypeToExpandTo ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

For types supported by the target, this is an identity function. For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.

Definition at line 396 of file TargetLowering.h.

396  {
397  assert(!VT.isVector());
398  while (true) {
399  switch (getTypeAction(Context, VT)) {
400  case TypeLegal:
401  return VT;
402  case TypeExpandInteger:
403  VT = getTypeToTransformTo(Context, VT);
404  break;
405  default:
406  llvm_unreachable("Type is not legal nor is it to be expanded!");
407  }
408  }
409  }
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
assert(Globals.size() > 1)
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
MVT llvm::TargetLoweringBase::getTypeToPromoteTo ( unsigned  Op,
MVT  VT 
) const
inlineinherited

If the action for this operation is to promote, this method returns the ValueType to promote to.

Definition at line 611 of file TargetLowering.h.

611  {
612  assert(getOperationAction(Op, VT) == Promote &&
613  "This operation isn't promoted!");
614 
615  // See if this has an explicit type specified.
616  std::map<std::pair<unsigned, MVT::SimpleValueType>,
617  MVT::SimpleValueType>::const_iterator PTTI =
618  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
619  if (PTTI != PromoteToType.end()) return PTTI->second;
620 
621  assert((VT.isInteger() || VT.isFloatingPoint()) &&
622  "Cannot autopromote this type, add it with AddPromotedToType.");
623 
624  MVT NVT = VT;
625  do {
626  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
627  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
628  "Didn't find type to promote to!");
629  } while (!isTypeLegal(NVT) ||
630  getOperationAction(Op, NVT) == Promote);
631  return NVT;
632  }
std::map< std::pair< unsigned, MVT::SimpleValueType >, MVT::SimpleValueType > PromoteToType
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
EVT llvm::TargetLoweringBase::getTypeToTransformTo ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

For types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Definition at line 388 of file TargetLowering.h.

388  {
389  return getTypeConversion(Context, VT).second;
390  }
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
EVT llvm::TargetLoweringBase::getValueType ( Type Ty,
bool  AllowUnknown = false 
) const
inlineinherited

Return the EVT corresponding to this LLVM type. This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.

Definition at line 638 of file TargetLowering.h.

638  {
639  // Lower scalar pointers to native pointer types.
640  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
641  return getPointerTy(PTy->getAddressSpace());
642 
643  if (Ty->isVectorTy()) {
644  VectorType *VTy = cast<VectorType>(Ty);
645  Type *Elm = VTy->getElementType();
646  // Lower vectors of pointers to native pointer types.
647  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
648  EVT PointerTy(getPointerTy(PT->getAddressSpace()));
649  Elm = PointerTy.getTypeForEVT(Ty->getContext());
650  }
651 
652  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
653  VTy->getNumElements());
654  }
655  return EVT::getEVT(Ty, AllowUnknown);
656  }
void * PointerTy
Definition: GenericValue.h:23
virtual MVT getPointerTy(uint32_t=0) const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:275
RelocType Type
Definition: COFFYAML.cpp:285
const ValueTypeActionImpl& llvm::TargetLoweringBase::getValueTypeActions ( ) const
inlineinherited

Definition at line 367 of file TargetLowering.h.

367  {
368  return ValueTypeActions;
369  }
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
virtual MVT llvm::TargetLoweringBase::getVectorIdxTy ( ) const
inlinevirtualinherited

Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 169 of file TargetLowering.h.

169  {
170  return getPointerTy();
171  }
virtual MVT getPointerTy(uint32_t=0) const
unsigned TargetLoweringBase::getVectorTypeBreakdown ( LLVMContext Context,
EVT  VT,
EVT IntermediateVT,
unsigned &  NumIntermediates,
MVT RegisterVT 
) const
inherited

Vector types are broken down into some number of legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

Definition at line 1227 of file TargetLoweringBase.cpp.

1230  {
1231  unsigned NumElts = VT.getVectorNumElements();
1232 
1233  // If there is a wider vector type with the same element type as this one,
1234  // or a promoted vector type that has the same number of elements which
1235  // are wider, then we should convert to that legal vector type.
1236  // This handles things like <2 x float> -> <4 x float> and
1237  // <4 x i1> -> <4 x i32>.
1238  LegalizeTypeAction TA = getTypeAction(Context, VT);
1239  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1240  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1241  if (isTypeLegal(RegisterEVT)) {
1242  IntermediateVT = RegisterEVT;
1243  RegisterVT = RegisterEVT.getSimpleVT();
1244  NumIntermediates = 1;
1245  return 1;
1246  }
1247  }
1248 
1249  // Figure out the right, legal destination reg to copy into.
1250  EVT EltTy = VT.getVectorElementType();
1251 
1252  unsigned NumVectorRegs = 1;
1253 
1254  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1255  // could break down into LHS/RHS like LegalizeDAG does.
1256  if (!isPowerOf2_32(NumElts)) {
1257  NumVectorRegs = NumElts;
1258  NumElts = 1;
1259  }
1260 
1261  // Divide the input until we get to a supported size. This will always
1262  // end with a scalar if the target doesn't support vectors.
1263  while (NumElts > 1 && !isTypeLegal(
1264  EVT::getVectorVT(Context, EltTy, NumElts))) {
1265  NumElts >>= 1;
1266  NumVectorRegs <<= 1;
1267  }
1268 
1269  NumIntermediates = NumVectorRegs;
1270 
1271  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1272  if (!isTypeLegal(NewVT))
1273  NewVT = EltTy;
1274  IntermediateVT = NewVT;
1275 
1276  MVT DestVT = getRegisterType(Context, NewVT);
1277  RegisterVT = DestVT;
1278  unsigned NewVTSize = NewVT.getSizeInBits();
1279 
1280  // Convert sizes such as i33 to i64.
1281  if (!isPowerOf2_32(NewVTSize))
1282  NewVTSize = NextPowerOf2(NewVTSize);
1283 
1284  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1285  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1286 
1287  // Otherwise, promotion or legal types use the same number of registers as
1288  // the vector decimated to the appropriate level.
1289  return NumVectorRegs;
1290 }
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
unsigned getSizeInBits() const
EVT getVectorElementType() const
Definition: ValueTypes.h:217
bool isTypeLegal(EVT VT) const
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
uint64_t NextPowerOf2(uint64_t A)
Definition: MathExtras.h:567
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
MVT getSimpleVT() const
Definition: ValueTypes.h:204
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
SDValue ARMTargetLowering::getVFPCmp ( SDValue  LHS,
SDValue  RHS,
SelectionDAG DAG,
SDLoc  dl 
) const
private

Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.

Definition at line 3210 of file ARMISelLowering.cpp.

3211  {
3212  SDValue Cmp;
3213  if (!isFloatingPointZero(RHS))
3214  Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3215  else
3216  Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3217  return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3218 }
static bool isFloatingPointZero(SDValue Op)
isFloatingPointZero - Return true if this is +0.0.
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
void ARMTargetLowering::HandleByVal ( CCState State,
unsigned &  size,
unsigned  Align 
) const
overrideprivatevirtual

HandleByVal - Target-specific cleanup for ByVal support.

HandleByVal - Every parameter after a byval parameter is passed on the stack. Remember the next parameter register to allocate, and then confiscate the rest of the parameter registers to insure this.

Reimplemented from llvm::TargetLowering.

Definition at line 1801 of file ARMISelLowering.cpp.

1802  {
1803  unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1804  assert((State->getCallOrPrologue() == Prologue ||
1805  State->getCallOrPrologue() == Call) &&
1806  "unhandled ParmContext");
1807 
1808  if ((ARM::R0 <= reg) && (reg <= ARM::R3)) {
1809  if (Subtarget->isAAPCS_ABI() && Align > 4) {
1810  unsigned AlignInRegs = Align / 4;
1811  unsigned Waste = (ARM::R4 - reg) % AlignInRegs;
1812  for (unsigned i = 0; i < Waste; ++i)
1813  reg = State->AllocateReg(GPRArgRegs, 4);
1814  }
1815  if (reg != 0) {
1816  unsigned excess = 4 * (ARM::R4 - reg);
1817 
1818  // Special case when NSAA != SP and parameter size greater than size of
1819  // all remained GPR regs. In that case we can't split parameter, we must
1820  // send it to stack. We also must set NCRN to R4, so waste all
1821  // remained registers.
1822  const unsigned NSAAOffset = State->getNextStackOffset();
1823  if (Subtarget->isAAPCS_ABI() && NSAAOffset != 0 && size > excess) {
1824  while (State->AllocateReg(GPRArgRegs, 4))
1825  ;
1826  return;
1827  }
1828 
1829  // First register for byval parameter is the first register that wasn't
1830  // allocated before this method call, so it would be "reg".
1831  // If parameter is small enough to be saved in range [reg, r4), then
1832  // the end (first after last) register would be reg + param-size-in-regs,
1833  // else parameter would be splitted between registers and stack,
1834  // end register would be r4 in this case.
1835  unsigned ByValRegBegin = reg;
1836  unsigned ByValRegEnd = (size < excess) ? reg + size/4 : (unsigned)ARM::R4;
1837  State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1838  // Note, first register is allocated in the beginning of function already,
1839  // allocate remained amount of registers we need.
1840  for (unsigned i = reg+1; i != ByValRegEnd; ++i)
1841  State->AllocateReg(GPRArgRegs, 4);
1842  // A byval parameter that is split between registers and memory needs its
1843  // size truncated here.
1844  // In the case where the entire structure fits in registers, we set the
1845  // size in memory to zero.
1846  if (size < excess)
1847  size = 0;
1848  else
1849  size -= excess;
1850  }
1851  }
1852 }
#define R4(n)
ParmContext getCallOrPrologue() const
void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd)
static const MCPhysReg GPRArgRegs[]
assert(Globals.size() > 1)
unsigned getNextStackOffset() const
const ARMSubtarget * Subtarget
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
bool isAAPCS_ABI() const
Definition: ARMSubtarget.h:395
unsigned AllocateReg(unsigned Reg)
bool llvm::TargetLoweringBase::hasBigEndianPartOrdering ( EVT  VT) const
inlineinherited

When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.

Definition at line 731 of file TargetLowering.h.

731  {
732  return isBigEndian() || VT == MVT::ppcf128;
733  }
bool llvm::TargetLoweringBase::hasExtractBitsInsn ( ) const
inlineinherited

Return true if the target has BitExtract instructions.

Definition at line 186 of file TargetLowering.h.

bool llvm::TargetLoweringBase::hasMultipleConditionRegisters ( ) const
inlineinherited

Return true if multiple condition registers are available.

Definition at line 181 of file TargetLowering.h.

181  {
183  }
virtual bool llvm::TargetLoweringBase::hasPairedLoad ( Type ,
unsigned &   
) const
inlinevirtualinherited

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.

This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).

In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1356 of file TargetLowering.h.

1357  {
1358  return false;
1359  }
virtual bool llvm::TargetLoweringBase::hasPairedLoad ( EVT  ,
unsigned &   
) const
inlinevirtualinherited

Specify maximum number of store instructions per memset call.

When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1361 of file TargetLowering.h.

1362  {
1363  return false;
1364  }
bool llvm::TargetLoweringBase::hasTargetDAGCombine ( ISD::NodeType  NT) const
inlineinherited

If true, the target has custom DAG combine transformations that it can perform for the specified node.

Definition at line 737 of file TargetLowering.h.

737  {
738  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
739  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
740  }
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
void TargetLoweringBase::initActions ( )
protectedinherited

Initialize all of the actions to default values.

Definition at line 733 of file TargetLoweringBase.cpp.

733  {
734  // All operations default to being supported.
735  memset(OpActions, 0, sizeof(OpActions));
736  memset(LoadExtActions, 0, sizeof(LoadExtActions));
742 
743  // Set default actions for various operations.
744  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
745  // Default all indexed load / store to expand.
746  for (unsigned IM = (unsigned)ISD::PRE_INC;
747  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
750  }
751 
752  // Most backends expect to see the node which just returns the value loaded.
755 
756  // These operations default to expand.
759 
760  // These library functions default to expand.
762 
763  // These operations default to expand for vector types.
764  if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
773  }
774  }
775 
776  // Most targets ignore the @llvm.prefetch intrinsic.
778 
779  // ConstantFP nodes default to expand. Targets can either change this to
780  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
781  // to optimize expansions for certain constants.
787 
788  // These library functions default to expand.
833 
834  // Default ISD::TRAP to expand (which turns it into abort).
836 
837  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
838  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
839  //
841 }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:622
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:625
void *memset(void *b, int c, size_t len);
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
int TargetLoweringBase::InstructionOpcodeToISD ( unsigned  Opcode) const
inherited

Get the ISD node that corresponds to the Instruction class opcode.

Definition at line 1353 of file TargetLoweringBase.cpp.

1353  {
1354  enum InstructionOpcodes {
1355 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1356 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1357 #include "llvm/IR/Instruction.def"
1358  };
1359  switch (static_cast<InstructionOpcodes>(Opcode)) {
1360  case Ret: return 0;
1361  case Br: return 0;
1362  case Switch: return 0;
1363  case IndirectBr: return 0;
1364  case Invoke: return 0;
1365  case Resume: return 0;
1366  case Unreachable: return 0;
1367  case Add: return ISD::ADD;
1368  case FAdd: return ISD::FADD;
1369  case Sub: return ISD::SUB;
1370  case FSub: return ISD::FSUB;
1371  case Mul: return ISD::MUL;
1372  case FMul: return ISD::FMUL;
1373  case UDiv: return ISD::UDIV;
1374  case SDiv: return ISD::SDIV;
1375  case FDiv: return ISD::FDIV;
1376  case URem: return ISD::UREM;
1377  case SRem: return ISD::SREM;
1378  case FRem: return ISD::FREM;
1379  case Shl: return ISD::SHL;
1380  case LShr: return ISD::SRL;
1381  case AShr: return ISD::SRA;
1382  case And: return ISD::AND;
1383  case Or: return ISD::OR;
1384  case Xor: return ISD::XOR;
1385  case Alloca: return 0;
1386  case Load: return ISD::LOAD;
1387  case Store: return ISD::STORE;
1388  case GetElementPtr: return 0;
1389  case Fence: return 0;
1390  case AtomicCmpXchg: return 0;
1391  case AtomicRMW: return 0;
1392  case Trunc: return ISD::TRUNCATE;
1393  case ZExt: return ISD::ZERO_EXTEND;
1394  case SExt: return ISD::SIGN_EXTEND;
1395  case FPToUI: return ISD::FP_TO_UINT;
1396  case FPToSI: return ISD::FP_TO_SINT;
1397  case UIToFP: return ISD::UINT_TO_FP;
1398  case SIToFP: return ISD::SINT_TO_FP;
1399  case FPTrunc: return ISD::FP_ROUND;
1400  case FPExt: return ISD::FP_EXTEND;
1401  case PtrToInt: return ISD::BITCAST;
1402  case IntToPtr: return ISD::BITCAST;
1403  case BitCast: return ISD::BITCAST;
1404  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1405  case ICmp: return ISD::SETCC;
1406  case FCmp: return ISD::SETCC;
1407  case PHI: return 0;
1408  case Call: return 0;
1409  case Select: return ISD::SELECT;
1410  case UserOp1: return 0;
1411  case UserOp2: return 0;
1412  case VAArg: return 0;
1414  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1415  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1416  case ExtractValue: return ISD::MERGE_VALUES;
1417  case InsertValue: return ISD::MERGE_VALUES;
1418  case LandingPad: return 0;
1419  }
1420 
1421  llvm_unreachable("Unknown instruction type encountered!");
1422 }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
static ConstantInt * ExtractElement(Constant *V, Constant *Idx)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1870
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
Definition: APInt.h:1875
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1865
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
bool llvm::TargetLoweringBase::isBigEndian ( ) const
inlineinherited

Definition at line 153 of file TargetLowering.h.

153 { return !IsLittleEndian; }
bool IsLittleEndian
True if this is a little endian target.
bool llvm::TargetLoweringBase::isCondCodeLegal ( ISD::CondCode  CC,
MVT  VT 
) const
inlineinherited

Return true if the specified condition code is legal on this target.

Definition at line 602 of file TargetLowering.h.

602  {
603  return
604  getCondCodeAction(CC, VT) == Legal ||
605  getCondCodeAction(CC, VT) == Custom;
606  }
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
bool TargetLowering::isConstFalseVal ( const SDNode N) const
inherited

Return if the N is a constant or constant vector equal to the false value from getBooleanContents().

Definition at line 1179 of file TargetLowering.cpp.

1179  {
1180  if (!N)
1181  return false;
1182 
1183  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1184  if (!CN) {
1186  if (!BV)
1187  return false;
1188 
1189  BitVector UndefElements;
1190  CN = BV->getConstantSplatNode(&UndefElements);
1191  // Only interested in constant splats, and we don't try to handle undef
1192  // elements in identifying boolean constants.
1193  if (!CN || UndefElements.none())
1194  return false;
1195  }
1196 
1198  return !CN->getAPIntValue()[0];
1199 
1200  return CN->isNullValue();
1201 }
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:152
ConstantSDNode * getConstantSplatNode(BitVector *UndefElements=nullptr) const
Returns the splatted constant or null if this is not a constant splat.
EVT getValueType(unsigned ResNo) const
const APInt & getAPIntValue() const
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
#define N
bool TargetLowering::isConstTrueVal ( const SDNode N) const
inherited

Return if the N is a constant or constant vector equal to the true value from getBooleanContents().

Definition at line 1149 of file TargetLowering.cpp.

1149  {
1150  if (!N)
1151  return false;
1152 
1153  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1154  if (!CN) {
1156  if (!BV)
1157  return false;
1158 
1159  BitVector UndefElements;
1160  CN = BV->getConstantSplatNode(&UndefElements);
1161  // Only interested in constant splats, and we don't try to handle undef
1162  // elements in identifying boolean constants.
1163  if (!CN || UndefElements.none())
1164  return false;
1165  }
1166 
1167  switch (getBooleanContents(N->getValueType(0))) {
1169  return CN->getAPIntValue()[0];
1171  return CN->isOne();
1173  return CN->isAllOnesValue();
1174  }
1175 
1176  llvm_unreachable("Invalid boolean contents");
1177 }
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:152
ConstantSDNode * getConstantSplatNode(BitVector *UndefElements=nullptr) const
Returns the splatted constant or null if this is not a constant splat.
bool isAllOnesValue() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
const APInt & getAPIntValue() const
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
#define N
virtual bool llvm::TargetLowering::isDesirableToCommuteWithShift ( const SDNode N) const
inlinevirtualinherited

Return true if it is profitable to move a following shift through this.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 2060 of file TargetLowering.h.

2060  {
2061  return true;
2062  }
virtual bool llvm::TargetLowering::IsDesirableToPromoteOp ( SDValue  ,
EVT  
) const
inlinevirtualinherited

This method query the target whether it is beneficial for dag combiner to promote the specified node. If true, it should return the desired promotion type by reference.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2084 of file TargetLowering.h.

2084  {
2085  return false;
2086  }
bool ARMTargetLowering::isDesirableToTransformToIntegerOp ( unsigned  Opc,
EVT  VT 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 9694 of file ARMISelLowering.cpp.

9695  {
9696  return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9697 }
bool ARMTargetLowering::IsEligibleForTailCallOptimization ( SDValue  Callee,
CallingConv::ID  CalleeCC,
bool  isVarArg,
bool  isCalleeStructRet,
bool  isCallerStructRet,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
const SmallVectorImpl< SDValue > &  OutVals,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SelectionDAG DAG 
) const
private

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization. Targets which want to do tail call optimization should implement this function.

Definition at line 1902 of file ARMISelLowering.cpp.

1910  {
1911  const Function *CallerF = DAG.getMachineFunction().getFunction();
1912  CallingConv::ID CallerCC = CallerF->getCallingConv();
1913  bool CCMatch = CallerCC == CalleeCC;
1914 
1915  // Look for obvious safe cases to perform tail call optimization that do not
1916  // require ABI changes. This is what gcc calls sibcall.
1917 
1918  // Do not sibcall optimize vararg calls unless the call site is not passing
1919  // any arguments.
1920  if (isVarArg && !Outs.empty())
1921  return false;
1922 
1923  // Exception-handling functions need a special set of instructions to indicate
1924  // a return to the hardware. Tail-calling another function would probably
1925  // break this.
1926  if (CallerF->hasFnAttribute("interrupt"))
1927  return false;
1928 
1929  // Also avoid sibcall optimization if either caller or callee uses struct
1930  // return semantics.
1931  if (isCalleeStructRet || isCallerStructRet)
1932  return false;
1933 
1934  // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1935  // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1936  // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1937  // support in the assembler and linker to be used. This would need to be
1938  // fixed to fully support tail calls in Thumb1.
1939  //
1940  // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1941  // LR. This means if we need to reload LR, it takes an extra instructions,
1942  // which outweighs the value of the tail call; but here we don't know yet
1943  // whether LR is going to be used. Probably the right approach is to
1944  // generate the tail call here and turn it back into CALL/RET in
1945  // emitEpilogue if LR is used.
1946 
1947  // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1948  // but we need to make sure there are enough registers; the only valid
1949  // registers are the 4 used for parameters. We don't currently do this
1950  // case.
1951  if (Subtarget->isThumb1Only())
1952  return false;
1953 
1954  // If the calling conventions do not match, then we'd better make sure the
1955  // results are returned in the same way as what the caller expects.
1956  if (!CCMatch) {
1958  ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1959  getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1960  CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1961 
1963  ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1964  getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1965  CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1966 
1967  if (RVLocs1.size() != RVLocs2.size())
1968  return false;
1969  for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1970  if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1971  return false;
1972  if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1973  return false;
1974  if (RVLocs1[i].isRegLoc()) {
1975  if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1976  return false;
1977  } else {
1978  if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1979  return false;
1980  }
1981  }
1982  }
1983 
1984  // If Caller's vararg or byval argument has been split between registers and
1985  // stack, do not perform tail call, since part of the argument is in caller's
1986  // local frame.
1987  const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
1988  getInfo<ARMFunctionInfo>();
1989  if (AFI_Caller->getArgRegsSaveSize())
1990  return false;
1991 
1992  // If the callee takes no arguments then go on to check the results of the
1993  // call.
1994  if (!Outs.empty()) {
1995  // Check if stack adjustment is needed. For now, do not do this if any
1996  // argument is passed on the stack.
1998  ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1999  getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
2000  CCInfo.AnalyzeCallOperands(Outs,
2001  CCAssignFnForNode(CalleeCC, false, isVarArg));
2002  if (CCInfo.getNextStackOffset()) {
2003  MachineFunction &MF = DAG.getMachineFunction();
2004 
2005  // Check if the arguments are already laid out in the right way as
2006  // the caller's fixed stack objects.
2007  MachineFrameInfo *MFI = MF.getFrameInfo();
2008  const MachineRegisterInfo *MRI = &MF.getRegInfo();
2010  for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2011  i != e;
2012  ++i, ++realArgIdx) {
2013  CCValAssign &VA = ArgLocs[i];
2014  EVT RegVT = VA.getLocVT();
2015  SDValue Arg = OutVals[realArgIdx];
2016  ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2017  if (VA.getLocInfo() == CCValAssign::Indirect)
2018  return false;
2019  if (VA.needsCustom()) {
2020  // f64 and vector types are split into multiple registers or
2021  // register/stack-slot combinations. The types will not match
2022  // the registers; give up on memory f64 refs until we figure
2023  // out what to do about this.
2024  if (!VA.isRegLoc())
2025  return false;
2026  if (!ArgLocs[++i].isRegLoc())
2027  return false;
2028  if (RegVT == MVT::v2f64) {
2029  if (!ArgLocs[++i].isRegLoc())
2030  return false;
2031  if (!ArgLocs[++i].isRegLoc())
2032  return false;
2033  }
2034  } else if (!VA.isRegLoc()) {
2035  if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2036  MFI, MRI, TII))
2037  return false;
2038  }
2039  }
2040  }
2041  }
2042 
2043  return true;
2044 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
LocInfo getLocInfo() const
const TargetMachine & getTargetMachine() const
const Function * getFunction() const
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
static bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII)
bool isRegLoc() const
CallingConv::ID getCallingConv() const
Definition: Function.h:161
const HexagonInstrInfo * TII
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Abstract Stack Frame Information.
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
MVT getLocVT() const
bool needsCustom() const
virtual const TargetInstrInfo * getInstrInfo() const
CCValAssign - Represent assignment of one arg/retval to a location.
const ARMSubtarget * Subtarget
MachineFrameInfo * getFrameInfo()
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:200
MachineRegisterInfo & getRegInfo()
CCAssignFn * CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const
unsigned getLocMemOffset() const
unsigned getArgRegsSaveSize(unsigned Align=0) const
virtual bool llvm::TargetLoweringBase::isFAbsFree ( EVT  VT) const
inlinevirtualinherited

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 1382 of file TargetLowering.h.

1382  {
1383  assert(VT.isFloatingPoint());
1384  return false;
1385  }
assert(Globals.size() > 1)
bool llvm::ARMTargetLowering::isFMAFasterThanFMulAndFAdd ( EVT  VT) const
inlineoverrideprivatevirtual

isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd instructions. fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

ARM supports both fused and unfused multiply-add operations; we already lower a pair of fmul and fadd to the latter so it's not clear that there would be a gain or that the gain would be worthwhile enough to risk correctness bugs.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 488 of file ARMISelLowering.h.

488 { return false; }
virtual bool llvm::TargetLoweringBase::isFNegFree ( EVT  VT) const
inlinevirtualinherited

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 1375 of file TargetLowering.h.

1375  {
1376  assert(VT.isFloatingPoint());
1377  return false;
1378  }
assert(Globals.size() > 1)
bool ARMTargetLowering::isFPImmLegal ( const APFloat Imm,
EVT  VT 
) const
overridevirtual

isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively. If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10656 of file ARMISelLowering.cpp.

10656  {
10657  if (!Subtarget->hasVFP3())
10658  return false;
10659  if (VT == MVT::f32)
10660  return ARM_AM::getFP32Imm(Imm) != -1;
10661  if (VT == MVT::f64)
10662  return ARM_AM::getFP64Imm(Imm) != -1;
10663  return false;
10664 }
bool hasVFP3() const
Definition: ARMSubtarget.h:308
static int getFP32Imm(const APInt &Imm)
static int getFP64Imm(const APInt &Imm)
const ARMSubtarget * Subtarget
bool TargetLowering::isGAPlusOffset ( SDNode N,
const GlobalValue *&  GA,
int64_t &  Offset 
) const
virtualinherited

Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2005 of file TargetLowering.cpp.

2006  {
2007  if (isa<GlobalAddressSDNode>(N)) {
2008  GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2009  GA = GASD->getGlobal();
2010  Offset += GASD->getOffset();
2011  return true;
2012  }
2013 
2014  if (N->getOpcode() == ISD::ADD) {
2015  SDValue N1 = N->getOperand(0);
2016  SDValue N2 = N->getOperand(1);
2017  if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2019  if (V) {
2020  Offset += V->getSExtValue();
2021  return true;
2022  }
2023  } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2025  if (V) {
2026  Offset += V->getSExtValue();
2027  return true;
2028  }
2029  }
2030  }
2031 
2032  return false;
2033 }
const GlobalValue * getGlobal() const
unsigned getOpcode() const
const SDValue & getOperand(unsigned Num) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
int64_t getSExtValue() const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
#define N
bool llvm::TargetLoweringBase::isIndexedLoadLegal ( unsigned  IdxMode,
EVT  VT 
) const
inlineinherited

Return true if the specified indexed load is legal on this target.

Definition at line 561 of file TargetLowering.h.

561  {
562  return VT.isSimple() &&
563  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
564  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
565  }
LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const
bool llvm::TargetLoweringBase::isIndexedStoreLegal ( unsigned  IdxMode,
EVT  VT 
) const
inlineinherited

Return true if the specified indexed load is legal on this target.

Definition at line 579 of file TargetLowering.h.

579  {
580  return VT.isSimple() &&
581  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
582  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
583  }
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
bool TargetLowering::isInTailCallPosition ( SelectionDAG DAG,
SDNode Node,
SDValue Chain 
) const
inherited

Check whether a given call node is in tail position within its function. If so, it sets Chain to the input chain of the tail call.

Definition at line 48 of file TargetLowering.cpp.

49  {
50  const Function *F = DAG.getMachineFunction().getFunction();
51 
52  // Conservatively require the attributes of the call to match those of
53  // the return. Ignore noalias because it doesn't affect the call sequence.
54  AttributeSet CallerAttrs = F->getAttributes();
55  if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56  .removeAttribute(Attribute::NoAlias).hasAttributes())
57  return false;
58 
59  // It's not safe to eliminate the sign / zero extension of the return value.
62  return false;
63 
64  // Check if the only use is a function return node.
65  return isUsedByReturnOnly(Node, Chain);
66 }
Sign extended before/after call.
Definition: Attributes.h:101
F(f)
const Function * getFunction() const
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Considered to not alias after call.
Definition: Attributes.h:82
Zero extended before/after call.
Definition: Attributes.h:114
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
bool llvm::TargetLoweringBase::isIntDivCheap ( ) const
inlineinherited

Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

Definition at line 215 of file TargetLowering.h.

215 { return IntDivIsCheap; }
bool llvm::TargetLoweringBase::isJumpExpensive ( ) const
inlineinherited

Return true if Flow Control is an expensive operation that should be avoided.

Definition at line 231 of file TargetLowering.h.

231 { return JumpIsExpensive; }
bool ARMTargetLowering::isLegalAddImmediate ( int64_t  Imm) const
overridevirtual

isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.

isLegalAddImmediate - Return true if the specified immediate is a legal add or sub immediate, that is the target has add or sub instructions which can add a register with the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10018 of file ARMISelLowering.cpp.

10018  {
10019  // Same encoding for add/sub, just flip the sign.
10020  int64_t AbsImm = llvm::abs64(Imm);
10021  if (!Subtarget->isThumb())
10022  return ARM_AM::getSOImmVal(AbsImm) != -1;
10023  if (Subtarget->isThumb2())
10024  return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10025  // Thumb1 only has 8-bit unsigned immediate.
10026  return AbsImm >= 0 && AbsImm <= 255;
10027 }
int64_t abs64(int64_t x)
Definition: MathExtras.h:607
bool isThumb() const
Definition: ARMSubtarget.h:400
static int getT2SOImmVal(unsigned Arg)
const ARMSubtarget * Subtarget
static int getSOImmVal(unsigned Arg)
bool isThumb2() const
Definition: ARMSubtarget.h:402
bool ARMTargetLowering::isLegalAddressingMode ( const AddrMode AM,
Type Ty 
) const
overridevirtual

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9941 of file ARMISelLowering.cpp.

9942  {
9943  EVT VT = getValueType(Ty, true);
9944  if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
9945  return false;
9946 
9947  // Can never fold addr of global into load/store.
9948  if (AM.BaseGV)
9949  return false;
9950 
9951  switch (AM.Scale) {
9952  case 0: // no scale reg, must be "r+i" or "r", or "i".
9953  break;
9954  case 1:
9955  if (Subtarget->isThumb1Only())
9956  return false;
9957  // FALL THROUGH.
9958  default:
9959  // ARM doesn't support any R+R*scale+imm addr modes.
9960  if (AM.BaseOffs)
9961  return false;
9962 
9963  if (!VT.isSimple())
9964  return false;
9965 
9966  if (Subtarget->isThumb2())
9967  return isLegalT2ScaledAddressingMode(AM, VT);
9968 
9969  int Scale = AM.Scale;
9970  switch (VT.getSimpleVT().SimpleTy) {
9971  default: return false;
9972  case MVT::i1:
9973  case MVT::i8:
9974  case MVT::i32:
9975  if (Scale < 0) Scale = -Scale;
9976  if (Scale == 1)
9977  return true;
9978  // r + r << imm
9979  return isPowerOf2_32(Scale & ~1);
9980  case MVT::i16:
9981  case MVT::i64:
9982  // r + r
9983  if (((unsigned)AM.HasBaseReg + Scale) <= 2)
9984  return true;
9985  return false;
9986 
9987  case MVT::isVoid:
9988  // Note, we allow "void" uses (basically, uses that aren't loads or
9989  // stores), because arm allows folding a scale into many arithmetic
9990  // operations. This should be made more precise and revisited later.
9991 
9992  // Allow r << imm, but the imm has to be a multiple of two.
9993  if (Scale & 1) return false;
9994  return isPowerOf2_32(Scale);
9995  }
9996  }
9997  return true;
9998 }
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
SimpleValueType SimpleTy
const ARMSubtarget * Subtarget
bool isThumb2() const
Definition: ARMSubtarget.h:402
static bool isLegalAddressImmediate(int64_t V, EVT VT, const ARMSubtarget *Subtarget)
bool isSimple() const
Definition: ValueTypes.h:95
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const
MVT getSimpleVT() const
Definition: ValueTypes.h:204
bool ARMTargetLowering::isLegalICmpImmediate ( int64_t  Imm) const
overridevirtual

isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10004 of file ARMISelLowering.cpp.

10004  {
10005  // Thumb2 and ARM modes can use cmn for negative immediates.
10006  if (!Subtarget->isThumb())
10007  return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
10008  if (Subtarget->isThumb2())
10009  return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
10010  // Thumb1 doesn't have cmn, and only 8-bit immediates.
10011  return Imm >= 0 && Imm <= 255;
10012 }
int64_t abs64(int64_t x)
Definition: MathExtras.h:607
bool isThumb() const
Definition: ARMSubtarget.h:400
static int getT2SOImmVal(unsigned Arg)
const ARMSubtarget * Subtarget
static int getSOImmVal(unsigned Arg)
bool isThumb2() const
Definition: ARMSubtarget.h:402
bool TargetLoweringBase::isLegalRC ( const TargetRegisterClass RC) const
protectedinherited

Return true if the value types that can be represented by the specified register class are all legal.

isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.

Definition at line 934 of file TargetLoweringBase.cpp.

934  {
935  for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
936  I != E; ++I) {
937  if (isTypeLegal(*I))
938  return true;
939  }
940  return false;
941 }
vt_iterator vt_end() const
bool isTypeLegal(EVT VT) const
#define I(x, y, z)
Definition: MD5.cpp:54
vt_iterator vt_begin() const
bool ARMTargetLowering::isLegalT2ScaledAddressingMode ( const AddrMode AM,
EVT  VT 
) const

Definition at line 9906 of file ARMISelLowering.cpp.

9907  {
9908  int Scale = AM.Scale;
9909  if (Scale < 0)
9910  return false;
9911 
9912  switch (VT.getSimpleVT().SimpleTy) {
9913  default: return false;
9914  case MVT::i1:
9915  case MVT::i8:
9916  case MVT::i16:
9917  case MVT::i32:
9918  if (Scale == 1)
9919  return true;
9920  // r + r << imm
9921  Scale = Scale & ~1;
9922  return Scale == 2 || Scale == 4 || Scale == 8;
9923  case MVT::i64:
9924  // r + r
9925  if (((unsigned)AM.HasBaseReg + Scale) <= 2)
9926  return true;
9927  return false;
9928  case MVT::isVoid:
9929  // Note, we allow "void" uses (basically, uses that aren't loads or
9930  // stores), because arm allows folding a scale into many arithmetic
9931  // operations. This should be made more precise and revisited later.
9932 
9933  // Allow r << imm, but the imm has to be a multiple of two.
9934  if (Scale & 1) return false;
9935  return isPowerOf2_32(Scale);
9936  }
9937 }
SimpleValueType SimpleTy
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
MVT getSimpleVT() const
Definition: ValueTypes.h:204
bool llvm::TargetLoweringBase::isLittleEndian ( ) const
inlineinherited

Definition at line 154 of file TargetLowering.h.

154 { return IsLittleEndian; }
bool IsLittleEndian
True if this is a little endian target.
virtual bool llvm::TargetLoweringBase::isLoadBitCastBeneficial ( EVT  ,
EVT   
) const
inlinevirtualinherited

isLoadBitCastBeneficial() - Return true if the following transform is beneficial. fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 246 of file TargetLowering.h.

246  {
247  return true;
248  }
bool llvm::TargetLoweringBase::isLoadExtLegal ( unsigned  ExtType,
EVT  VT 
) const
inlineinherited

Return true if the specified load with extension is legal on this target.

Definition at line 527 of file TargetLowering.h.

527  {
528  return VT.isSimple() &&
529  getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
530  }
LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const
bool llvm::TargetLoweringBase::isMaskAndBranchFoldingLegal ( ) const
inlineinherited

Return if the target supports combining a chain like:

%andResult = and %val1, #imm-with-one-bit-set;
%icmpResult = icmp %andResult, 0
br i1 %icmpResult, label %dest1, label %dest2

into a single machine instruction of a form like:

brOnBitSet %register, #bitNumber, dest

Definition at line 261 of file TargetLowering.h.

261  {
263  }
virtual bool llvm::TargetLoweringBase::isNarrowingProfitable ( EVT  ,
EVT   
) const
inlinevirtualinherited

Return true if it's profitable to narrow operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1402 of file TargetLowering.h.

1402  {
1403  return false;
1404  }
bool llvm::ARMTargetLowering::isNoopAddrSpaceCast ( unsigned  SrcAS,
unsigned  DestAS 
) const
inlineoverridevirtual

Returns true if a cast between SrcAS and DestAS is a noop.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 359 of file ARMISelLowering.h.

359  {
360  // Addrspacecasts are always noops.
361  return true;
362  }
bool ARMTargetLowering::isOffsetFoldingLegal ( const GlobalAddressSDNode GA) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 10635 of file ARMISelLowering.cpp.

10635  {
10636  // The ARM target isn't yet aware of offsets.
10637  return false;
10638 }
bool llvm::TargetLoweringBase::isOperationExpand ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. This is used to help guide high-level lowering decisions.

Definition at line 507 of file TargetLowering.h.

507  {
508  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
509  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isOperationLegal ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target.

Definition at line 512 of file TargetLowering.h.

512  {
513  return (VT == MVT::Other || isTypeLegal(VT)) &&
514  getOperationAction(Op, VT) == Legal;
515  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isOperationLegalOrCustom ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target or can be made legal with custom lowering. This is used to help guide high-level lowering decisions.

Definition at line 489 of file TargetLowering.h.

489  {
490  return (VT == MVT::Other || isTypeLegal(VT)) &&
491  (getOperationAction(Op, VT) == Legal ||
492  getOperationAction(Op, VT) == Custom);
493  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isOperationLegalOrPromote ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target or can be made legal using promotion. This is used to help guide high-level lowering decisions.

Definition at line 498 of file TargetLowering.h.

498  {
499  return (VT == MVT::Other || isTypeLegal(VT)) &&
500  (getOperationAction(Op, VT) == Legal ||
501  getOperationAction(Op, VT) == Promote);
502  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isPow2DivCheap ( ) const
inlineinherited

Return true if pow2 div is cheaper than a chain of srl/add/sra.

Definition at line 227 of file TargetLowering.h.

227 { return Pow2DivIsCheap; }
bool llvm::TargetLoweringBase::isPredictableSelectExpensive ( ) const
inlineinherited

Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

Definition at line 235 of file TargetLowering.h.

235  {
237  }
virtual bool llvm::TargetLoweringBase::isSafeMemOpType ( MVT  ) const
inlinevirtualinherited

Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.

This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.

Reimplemented in llvm::X86TargetLowering.

Definition at line 814 of file TargetLowering.h.

814 { return true; }
bool llvm::TargetLoweringBase::isSelectExpensive ( ) const
inlineinherited

Return true if the select operation is expensive for this target.

Definition at line 174 of file TargetLowering.h.

174 { return SelectIsExpensive; }
bool llvm::ARMTargetLowering::isSelectSupported ( SelectSupportKind  Kind) const
inlineoverridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 249 of file ARMISelLowering.h.

249  {
250  // ARM does not support scalar condition selects on vectors.
251  return (Kind != ScalarCondVectorVal);
252  }
Kind
Definition: YAMLIOTest.cpp:893
bool ARMTargetLowering::isShuffleMaskLegal ( const SmallVectorImpl< int > &  M,
EVT  VT 
) const
overridevirtual

isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 5264 of file ARMISelLowering.cpp.

5265  {
5266  if (VT.getVectorNumElements() == 4 &&
5267  (VT.is128BitVector() || VT.is64BitVector())) {
5268  unsigned PFIndexes[4];
5269  for (unsigned i = 0; i != 4; ++i) {
5270  if (M[i] < 0)
5271  PFIndexes[i] = 8;
5272  else
5273  PFIndexes[i] = M[i];
5274  }
5275 
5276  // Compute the index in the perfect shuffle table.
5277  unsigned PFTableIndex =
5278  PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5279  unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5280  unsigned Cost = (PFEntry >> 30);
5281 
5282  if (Cost <= 4)
5283  return true;
5284  }
5285 
5286  bool ReverseVEXT;
5287  unsigned Imm, WhichResult;
5288 
5289  unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5290  return (EltSize >= 32 ||
5291  ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5292  isVREVMask(M, VT, 64) ||
5293  isVREVMask(M, VT, 32) ||
5294  isVREVMask(M, VT, 16) ||
5295  isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5296  isVTBLMask(M, VT) ||
5297  isVTRNMask(M, VT, WhichResult) ||
5298  isVUZPMask(M, VT, WhichResult) ||
5299  isVZIPMask(M, VT, WhichResult) ||
5300  isVTRN_v_undef_Mask(M, VT, WhichResult) ||
5301  isVUZP_v_undef_Mask(M, VT, WhichResult) ||
5302  isVZIP_v_undef_Mask(M, VT, WhichResult) ||
5303  ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5304 }
static bool isVZIPMask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool isVTRNMask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool isVUZPMask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool isVREVMask(ArrayRef< int > M, EVT VT, unsigned BlockSize)
static bool isVZIP_v_undef_Mask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
EVT getVectorElementType() const
Definition: ValueTypes.h:217
static const unsigned PerfectShuffleTable[6561+1]
static bool isReverseMask(ArrayRef< int > M, EVT VT)
static bool isVTBLMask(ArrayRef< int > M, EVT VT)
static bool isVUZP_v_undef_Mask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:136
static bool isVTRN_v_undef_Mask(ArrayRef< int > M, EVT VT, unsigned &WhichResult)
bool is64BitVector() const
is64BitVector - Return true if this is a 64-bit vector type.
Definition: ValueTypes.h:131
static bool isSplatMask(const int *Mask, EVT VT)
static bool isVEXTMask(ArrayRef< int > M, EVT VT, bool &ReverseVEXT, unsigned &Imm)
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
bool llvm::TargetLoweringBase::isSlowDivBypassed ( ) const
inlineinherited

Returns true if target has indicated at least one type should be bypassed.

Definition at line 218 of file TargetLowering.h.

218 { return !BypassSlowDivWidths.empty(); }
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: DenseMap.h:68
virtual bool llvm::TargetLoweringBase::isTruncateFree ( Type ,
Type  
) const
inlinevirtualinherited

Return true if it's free to truncate a value of type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::MSP430TargetLowering, llvm::AMDGPUTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1302 of file TargetLowering.h.

1302  {
1303  return false;
1304  }
virtual bool llvm::TargetLoweringBase::isTruncateFree ( EVT  ,
EVT   
) const
inlinevirtualinherited

Reset the operation actions based on target options.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::MSP430TargetLowering, llvm::AMDGPUTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1315 of file TargetLowering.h.

1315  {
1316  return false;
1317  }
bool llvm::TargetLoweringBase::isTruncStoreLegal ( EVT  ValVT,
EVT  MemVT 
) const
inlineinherited

Return true if the specified store with truncation is legal on this target.

Definition at line 544 of file TargetLowering.h.

544  {
545  return isTypeLegal(ValVT) && MemVT.isSimple() &&
546  getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
547  }
LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const
bool isTypeLegal(EVT VT) const
virtual bool llvm::TargetLowering::isTypeDesirableForOp ( unsigned  ,
EVT  VT 
) const
inlinevirtualinherited

Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2068 of file TargetLowering.h.

2068  {
2069  // By default, assume all legal types are desirable.
2070  return isTypeLegal(VT);
2071  }
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isTypeLegal ( EVT  VT) const
inlineinherited

Return true if the target has native support for the specified value type. This means that it has a register that directly holds it without promotions or expansions.

Definition at line 341 of file TargetLowering.h.

341  {
342  assert(!VT.isSimple() ||
343  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
344  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
345  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
bool ARMTargetLowering::isUsedByReturnOnly ( SDNode N,
SDValue Chain 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2197 of file ARMISelLowering.cpp.

2197  {
2198  if (N->getNumValues() != 1)
2199  return false;
2200  if (!N->hasNUsesOfValue(1, 0))
2201  return false;
2202 
2203  SDValue TCChain = Chain;
2204  SDNode *Copy = *N->use_begin();
2205  if (Copy->getOpcode() == ISD::CopyToReg) {
2206  // If the copy has a glue operand, we conservatively assume it isn't safe to
2207  // perform a tail call.
2208  if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2209  return false;
2210  TCChain = Copy->getOperand(0);
2211  } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2212  SDNode *VMov = Copy;
2213  // f64 returned in a pair of GPRs.
2215  for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2216  UI != UE; ++UI) {
2217  if (UI->getOpcode() != ISD::CopyToReg)
2218  return false;
2219  Copies.insert(*UI);
2220  }
2221  if (Copies.size() > 2)
2222  return false;
2223 
2224  for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2225  UI != UE; ++UI) {
2226  SDValue UseChain = UI->getOperand(0);
2227  if (Copies.count(UseChain.getNode()))
2228  // Second CopyToReg
2229  Copy = *UI;
2230  else
2231  // First CopyToReg
2232  TCChain = UseChain;
2233  }
2234  } else if (Copy->getOpcode() == ISD::BITCAST) {
2235  // f32 returned in a single GPR.
2236  if (!Copy->hasOneUse())
2237  return false;
2238  Copy = *Copy->use_begin();
2239  if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2240  return false;
2241  TCChain = Copy->getOperand(0);
2242  } else {
2243  return false;
2244  }
2245 
2246  bool HasRet = false;
2247  for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2248  UI != UE; ++UI) {
2249  if (UI->getOpcode() != ARMISD::RET_FLAG &&
2250  UI->getOpcode() != ARMISD::INTRET_FLAG)
2251  return false;
2252  HasRet = true;
2253  }
2254 
2255  if (!HasRet)
2256  return false;
2257 
2258  Chain = TCChain;
2259  return true;
2260 }
bool hasOneUse() const
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:267
unsigned getOpcode() const
bool insert(PtrType Ptr)
Definition: SmallPtrSet.h:256
unsigned getNumOperands() const
const SDValue & getOperand(unsigned Num) const
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
unsigned getNumValues() const
SDNode * getNode() const
get the SDNode which holds the desired result
size_type size() const
Definition: SmallPtrSet.h:78
use_iterator use_begin() const
static use_iterator use_end()
SI Lower il Copies
virtual bool llvm::TargetLoweringBase::isVectorClearMaskLegal ( const SmallVectorImpl< int > &  ,
EVT   
) const
inlinevirtualinherited

Similar to isShuffleMaskLegal. This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.

Reimplemented in llvm::X86TargetLowering.

Definition at line 469 of file TargetLowering.h.

470  {
471  return false;
472  }
virtual bool llvm::TargetLoweringBase::isVectorShiftByScalarCheap ( Type Ty) const
inlinevirtualinherited

Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. On x86, for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1295 of file TargetLowering.h.

1295  {
1296  return false;
1297  }
bool ARMTargetLowering::isZExtFree ( SDValue  Val,
EVT  VT2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9773 of file ARMISelLowering.cpp.

9773  {
9774  if (Val.getOpcode() != ISD::LOAD)
9775  return false;
9776 
9777  EVT VT1 = Val.getValueType();
9778  if (!VT1.isSimple() || !VT1.isInteger() ||
9779  !VT2.isSimple() || !VT2.isInteger())
9780  return false;
9781 
9782  switch (VT1.getSimpleVT().SimpleTy) {
9783  default: break;
9784  case MVT::i1:
9785  case MVT::i8:
9786  case MVT::i16:
9787  // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
9788  return true;
9789  }
9790 
9791  return false;
9792 }
SimpleValueType SimpleTy
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
unsigned getOpcode() const
EVT getValueType() const
bool isSimple() const
Definition: ValueTypes.h:95
MVT getSimpleVT() const
Definition: ValueTypes.h:204
virtual bool llvm::TargetLoweringBase::isZExtFree ( Type ,
Type  
) const
inlinevirtualinherited

Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the value to Ty2 in the result register.

This does not necessarily include registers defined in unknown ways, such as incoming arguments, or copies from unknown virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to truncate instructions. e.g. on x86-64, all instructions that define 32-bit values implicit zero-extend the result out to 64 bits.

Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1327 of file TargetLowering.h.

1327  {
1328  return false;
1329  }
virtual bool llvm::TargetLoweringBase::isZExtFree ( EVT  ,
EVT   
) const
inlinevirtualinherited

Reset the operation actions based on target options.

Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1331 of file TargetLowering.h.

1331  {
1332  return false;
1333  }
void ARMTargetLowering::LowerAsmOperandForConstraint ( SDValue  Op,
std::string &  Constraint,
std::vector< SDValue > &  Ops,
SelectionDAG DAG 
) const
overridevirtual

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.

Reimplemented from llvm::TargetLowering.

Definition at line 10396 of file ARMISelLowering.cpp.

10399  {
10400  SDValue Result;
10401 
10402  // Currently only support length 1 constraints.
10403  if (Constraint.length() != 1) return;
10404 
10405  char ConstraintLetter = Constraint[0];
10406  switch (ConstraintLetter) {
10407  default: break;
10408  case 'j':
10409  case 'I': case 'J': case 'K': case 'L':
10410  case 'M': case 'N': case 'O':
10412  if (!C)
10413  return;
10414 
10415  int64_t CVal64 = C->getSExtValue();
10416  int CVal = (int) CVal64;
10417  // None of these constraints allow values larger than 32 bits. Check
10418  // that the value fits in an int.
10419  if (CVal != CVal64)
10420  return;
10421 
10422  switch (ConstraintLetter) {
10423  case 'j':
10424  // Constant suitable for movw, must be between 0 and
10425  // 65535.
10426  if (Subtarget->hasV6T2Ops())
10427  if (CVal >= 0 && CVal <= 65535)
10428  break;
10429  return;
10430  case 'I':
10431  if (Subtarget->isThumb1Only()) {
10432  // This must be a constant between 0 and 255, for ADD
10433  // immediates.
10434  if (CVal >= 0 && CVal <= 255)
10435  break;
10436  } else if (Subtarget->isThumb2()) {
10437  // A constant that can be used as an immediate value in a
10438  // data-processing instruction.
10439  if (ARM_AM::getT2SOImmVal(CVal) != -1)
10440  break;
10441  } else {
10442  // A constant that can be used as an immediate value in a
10443  // data-processing instruction.
10444  if (ARM_AM::getSOImmVal(CVal) != -1)
10445  break;
10446  }
10447  return;
10448 
10449  case 'J':
10450  if (Subtarget->isThumb()) { // FIXME thumb2
10451  // This must be a constant between -255 and -1, for negated ADD
10452  // immediates. This can be used in GCC with an "n" modifier that
10453  // prints the negated value, for use with SUB instructions. It is
10454  // not useful otherwise but is implemented for compatibility.
10455  if (CVal >= -255 && CVal <= -1)
10456  break;
10457  } else {
10458  // This must be a constant between -4095 and 4095. It is not clear
10459  // what this constraint is intended for. Implemented for
10460  // compatibility with GCC.
10461  if (CVal >= -4095 && CVal <= 4095)
10462  break;
10463  }
10464  return;
10465 
10466  case 'K':
10467  if (Subtarget->isThumb1Only()) {
10468  // A 32-bit value where only one byte has a nonzero value. Exclude
10469  // zero to match GCC. This constraint is used by GCC internally for
10470  // constants that can be loaded with a move/shift combination.
10471  // It is not useful otherwise but is implemented for compatibility.
10472  if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10473  break;
10474  } else if (Subtarget->isThumb2()) {
10475  // A constant whose bitwise inverse can be used as an immediate
10476  // value in a data-processing instruction. This can be used in GCC
10477  // with a "B" modifier that prints the inverted value, for use with
10478  // BIC and MVN instructions. It is not useful otherwise but is
10479  // implemented for compatibility.
10480  if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10481  break;
10482  } else {
10483  // A constant whose bitwise inverse can be used as an immediate
10484  // value in a data-processing instruction. This can be used in GCC
10485  // with a "B" modifier that prints the inverted value, for use with
10486  // BIC and MVN instructions. It is not useful otherwise but is
10487  // implemented for compatibility.
10488  if (ARM_AM::getSOImmVal(~CVal) != -1)
10489  break;
10490  }
10491  return;
10492 
10493  case 'L':
10494  if (Subtarget->isThumb1Only()) {
10495  // This must be a constant between -7 and 7,
10496  // for 3-operand ADD/SUB immediate instructions.
10497  if (CVal >= -7 && CVal < 7)
10498  break;
10499  } else if (Subtarget->isThumb2()) {
10500  // A constant whose negation can be used as an immediate value in a
10501  // data-processing instruction. This can be used in GCC with an "n"
10502  // modifier that prints the negated value, for use with SUB
10503  // instructions. It is not useful otherwise but is implemented for
10504  // compatibility.
10505  if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10506  break;
10507  } else {
10508  // A constant whose negation can be used as an immediate value in a
10509  // data-processing instruction. This can be used in GCC with an "n"
10510  // modifier that prints the negated value, for use with SUB
10511  // instructions. It is not useful otherwise but is implemented for
10512  // compatibility.
10513  if (ARM_AM::getSOImmVal(-CVal) != -1)
10514  break;
10515  }
10516  return;
10517 
10518  case 'M':
10519  if (Subtarget->isThumb()) { // FIXME thumb2
10520  // This must be a multiple of 4 between 0 and 1020, for
10521  // ADD sp + immediate.
10522  if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10523  break;
10524  } else {
10525  // A power of two or a constant between 0 and 32. This is used in
10526  // GCC for the shift amount on shifted register operands, but it is
10527  // useful in general for any shift amounts.
10528  if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10529  break;
10530  }
10531  return;
10532 
10533  case 'N':
10534  if (Subtarget->isThumb()) { // FIXME thumb2
10535  // This must be a constant between 0 and 31, for shift amounts.
10536  if (CVal >= 0 && CVal <= 31)
10537  break;
10538  }
10539  return;
10540 
10541  case 'O':
10542  if (Subtarget->isThumb()) { // FIXME thumb2
10543  // This must be a multiple of 4 between -508 and 508, for
10544  // ADD/SUB sp = sp + immediate.
10545  if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
10546  break;
10547  }
10548  return;
10549  }
10550  Result = DAG.getTargetConstant(CVal, Op.getValueType());
10551  break;
10552  }
10553 
10554  if (Result.getNode()) {
10555  Ops.push_back(Result);
10556  return;
10557  }
10558  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10559 }
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:290
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
bool isThumb() const
Definition: ARMSubtarget.h:400
static int getT2SOImmVal(unsigned Arg)
static bool isThumbImmShiftedVal(unsigned V)
SDNode * getNode() const
get the SDNode which holds the desired result
const ARMSubtarget * Subtarget
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
int64_t getSExtValue() const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
static int getSOImmVal(unsigned Arg)
bool isThumb2() const
Definition: ARMSubtarget.h:402
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
EVT getValueType() const
SDValue ARMTargetLowering::LowerBlockAddress ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2297 of file ARMISelLowering.cpp.

2298  {
2299  MachineFunction &MF = DAG.getMachineFunction();
2301  unsigned ARMPCLabelIndex = 0;
2302  SDLoc DL(Op);
2303  EVT PtrVT = getPointerTy();
2304  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2306  SDValue CPAddr;
2307  if (RelocM == Reloc::Static) {
2308  CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2309  } else {
2310  unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2311  ARMPCLabelIndex = AFI->createPICLabelUId();
2312  ARMConstantPoolValue *CPV =
2313  ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2314  ARMCP::CPBlockAddress, PCAdj);
2315  CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2316  }
2317  CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2318  SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2320  false, false, false, 0);
2321  if (RelocM == Reloc::Static)
2322  return Result;
2323  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2324  return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2325 }
Reloc::Model getRelocationModel() const
const TargetMachine & getTargetMachine() const
static MachinePointerInfo getConstantPool()
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
bool isThumb() const
Definition: ARMSubtarget.h:400
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:450
const ARMSubtarget * Subtarget
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
SDValue ARMTargetLowering::LowerBR_CC ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3638 of file ARMISelLowering.cpp.

3638  {
3639  SDValue Chain = Op.getOperand(0);
3640  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3641  SDValue LHS = Op.getOperand(2);
3642  SDValue RHS = Op.getOperand(3);
3643  SDValue Dest = Op.getOperand(4);
3644  SDLoc dl(Op);
3645 
3646  if (LHS.getValueType() == MVT::i32) {
3647  SDValue ARMcc;
3648  SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3649  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3650  return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3651  Chain, Dest, ARMcc, CCR, Cmp);
3652  }
3653 
3654  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3655 
3657  (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3658  CC == ISD::SETNE || CC == ISD::SETUNE)) {
3659  SDValue Result = OptimizeVFPBrcond(Op, DAG);
3660  if (Result.getNode())
3661  return Result;
3662  }
3663 
3664  ARMCC::CondCodes CondCode, CondCode2;
3665  FPCCToARMCC(CC, CondCode, CondCode2);
3666 
3667  SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3668  SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3669  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3670  SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3671  SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3672  SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3673  if (CondCode2 != ARMCC::AL) {
3674  ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3675  SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3676  Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3677  }
3678  return Res;
3679 }
SDValue getValue(unsigned R) const
const TargetMachine & getTargetMachine() const
SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl) const
Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
SDVTList getVTList(EVT VT)
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const
SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2)
FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getRegister(unsigned Reg, EVT VT)
SDValue ARMTargetLowering::LowerBR_JT ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3681 of file ARMISelLowering.cpp.

3681  {
3682  SDValue Chain = Op.getOperand(0);
3683  SDValue Table = Op.getOperand(1);
3684  SDValue Index = Op.getOperand(2);
3685  SDLoc dl(Op);
3686 
3687  EVT PTy = getPointerTy();
3688  JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3690  SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3691  SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3692  Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3693  Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3694  SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3695  if (Subtarget->isThumb2()) {
3696  // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3697  // which does another jump to the destination. This also makes it easier
3698  // to translate it to TBB / TBH later.
3699  // FIXME: This might not work if the function is extremely large.
3700  return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3701  Addr, Op.getOperand(2), JTI, UId);
3702  }
3704  Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3706  false, false, false, 0);
3707  Chain = Addr.getValue(1);
3708  Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3709  return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3710  } else {
3711  Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3713  false, false, false, 0);
3714  Chain = Addr.getValue(1);
3715  return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3716  }
3717 }
SDValue getValue(unsigned R) const
Reloc::Model getRelocationModel() const
static MachinePointerInfo getJumpTable()
const TargetMachine & getTargetMachine() const
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual MVT getPointerTy(uint32_t=0) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
const SDValue & getOperand(unsigned i) const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:444
const ARMSubtarget * Subtarget
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
bool isThumb2() const
Definition: ARMSubtarget.h:402
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue ARMTargetLowering::LowerBUILD_VECTOR ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
) const
private

Definition at line 4908 of file ARMISelLowering.cpp.

4909  {
4910  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
4911  SDLoc dl(Op);
4912  EVT VT = Op.getValueType();
4913 
4914  APInt SplatBits, SplatUndef;
4915  unsigned SplatBitSize;
4916  bool HasAnyUndefs;
4917  if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4918  if (SplatBitSize <= 64) {
4919  // Check if an immediate VMOV works.
4920  EVT VmovVT;
4921  SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4922  SplatUndef.getZExtValue(), SplatBitSize,
4923  DAG, VmovVT, VT.is128BitVector(),
4924  VMOVModImm);
4925  if (Val.getNode()) {
4926  SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
4927  return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4928  }
4929 
4930  // Try an immediate VMVN.
4931  uint64_t NegatedImm = (~SplatBits).getZExtValue();
4932  Val = isNEONModifiedImm(NegatedImm,
4933  SplatUndef.getZExtValue(), SplatBitSize,
4934  DAG, VmovVT, VT.is128BitVector(),
4935  VMVNModImm);
4936  if (Val.getNode()) {
4937  SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
4938  return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4939  }
4940 
4941  // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
4942  if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
4943  int ImmVal = ARM_AM::getFP32Imm(SplatBits);
4944  if (ImmVal != -1) {
4945  SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4946  return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
4947  }
4948  }
4949  }
4950  }
4951 
4952  // Scan through the operands to see if only one value is used.
4953  //
4954  // As an optimisation, even if more than one value is used it may be more
4955  // profitable to splat with one value then change some lanes.
4956  //
4957  // Heuristically we decide to do this if the vector has a "dominant" value,
4958  // defined as splatted to more than half of the lanes.
4959  unsigned NumElts = VT.getVectorNumElements();
4960  bool isOnlyLowElement = true;
4961  bool usesOnlyOneValue = true;
4962  bool hasDominantValue = false;
4963  bool isConstant = true;
4964 
4965  // Map of the number of times a particular SDValue appears in the
4966  // element list.
4967  DenseMap<SDValue, unsigned> ValueCounts;
4968  SDValue Value;
4969  for (unsigned i = 0; i < NumElts; ++i) {
4970  SDValue V = Op.getOperand(i);
4971  if (V.getOpcode() == ISD::UNDEF)
4972  continue;
4973  if (i > 0)
4974  isOnlyLowElement = false;
4975  if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4976  isConstant = false;
4977 
4978  ValueCounts.insert(std::make_pair(V, 0));
4979  unsigned &Count = ValueCounts[V];
4980 
4981  // Is this value dominant? (takes up more than half of the lanes)
4982  if (++Count > (NumElts / 2)) {
4983  hasDominantValue = true;
4984  Value = V;
4985  }
4986  }
4987  if (ValueCounts.size() != 1)
4988  usesOnlyOneValue = false;
4989  if (!Value.getNode() && ValueCounts.size() > 0)
4990  Value = ValueCounts.begin()->first;
4991 
4992  if (ValueCounts.size() == 0)
4993  return DAG.getUNDEF(VT);
4994 
4995  // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
4996  // Keep going if we are hitting this case.
4997  if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
4998  return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
4999 
5000  unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5001 
5002  // Use VDUP for non-constant splats. For f32 constant splats, reduce to
5003  // i32 and try again.
5004  if (hasDominantValue && EltSize <= 32) {
5005  if (!isConstant) {
5006  SDValue N;
5007 
5008  // If we are VDUPing a value that comes directly from a vector, that will
5009  // cause an unnecessary move to and from a GPR, where instead we could
5010  // just use VDUPLANE. We can only do this if the lane being extracted
5011  // is at a constant index, as the VDUP from lane instructions only have
5012  // constant-index forms.
5013  if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5014  isa<ConstantSDNode>(Value->getOperand(1))) {
5015  // We need to create a new undef vector to use for the VDUPLANE if the
5016  // size of the vector from which we get the value is different than the
5017  // size of the vector that we need to create. We will insert the element
5018  // such that the register coalescer will remove unnecessary copies.
5019  if (VT != Value->getOperand(0).getValueType()) {
5020  ConstantSDNode *constIndex;
5021  constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
5022  assert(constIndex && "The index is not a constant!");
5023  unsigned index = constIndex->getAPIntValue().getLimitedValue() %
5024  VT.getVectorNumElements();
5025  N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5026  DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5027  Value, DAG.getConstant(index, MVT::i32)),
5028  DAG.getConstant(index, MVT::i32));
5029  } else
5030  N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5031  Value->getOperand(0), Value->getOperand(1));
5032  } else
5033  N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5034 
5035  if (!usesOnlyOneValue) {
5036  // The dominant value was splatted as 'N', but we now have to insert
5037  // all differing elements.
5038  for (unsigned I = 0; I < NumElts; ++I) {
5039  if (Op.getOperand(I) == Value)
5040  continue;
5042  Ops.push_back(N);
5043  Ops.push_back(Op.getOperand(I));
5044  Ops.push_back(DAG.getConstant(I, MVT::i32));
5045  N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5046  }
5047  }
5048  return N;
5049  }
5052  for (unsigned i = 0; i < NumElts; ++i)
5053  Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
5054  Op.getOperand(i)));
5055  EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
5056  SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5057  Val = LowerBUILD_VECTOR(Val, DAG, ST);
5058  if (Val.getNode())
5059  return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5060  }
5061  if (usesOnlyOneValue) {
5062  SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
5063  if (isConstant && Val.getNode())
5064  return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
5065  }
5066  }
5067 
5068  // If all elements are constants and the case above didn't get hit, fall back
5069  // to the default expansion, which will generate a load from the constant
5070  // pool.
5071  if (isConstant)
5072  return SDValue();
5073 
5074  // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5075  if (NumElts >= 4) {
5076  SDValue shuffle = ReconstructShuffle(Op, DAG);
5077  if (shuffle != SDValue())
5078  return shuffle;
5079  }
5080 
5081  // Vectors with 32- or 64-bit elements can be built by directly assigning
5082  // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5083  // will be legalized.
5084  if (EltSize >= 32) {
5085  // Do the expansion with floating-point types, since that is what the VFP
5086  // registers are defined to use, and since i64 is not legal.
5087  EVT EltVT = EVT::getFloatingPointVT(EltSize);
5088  EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5090  for (unsigned i = 0; i < NumElts; ++i)
5091  Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
5092  SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5093  return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5094  }
5095 
5096  // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5097  // know the default expansion would otherwise fall back on something even
5098  // worse. For a vector with one or two non-undef values, that's
5099  // scalar_to_vector for the elements followed by a shuffle (provided the
5100  // shuffle is valid for the target) and materialization element by element
5101  // on the stack followed by a load for everything else.
5102  if (!isConstant && !usesOnlyOneValue) {
5103  SDValue Vec = DAG.getUNDEF(VT);
5104  for (unsigned i = 0 ; i < NumElts; ++i) {
5105  SDValue V = Op.getOperand(i);
5106  if (V.getOpcode() == ISD::UNDEF)
5107  continue;
5108  SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
5109  Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5110  }
5111  return Vec;
5112  }
5113 
5114  return SDValue();
5115 }
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1302
unsigned getOpcode() const
uint64_t getLimitedValue(uint64_t Limit=~0ULL) const
Definition: APInt.h:406
const SDValue & getOperand(unsigned Num) const
EVT getVectorElementType() const
Definition: ValueTypes.h:217
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
static int Value(bit_value_t V)
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const
const APInt & getAPIntValue() const
static int getFP32Imm(const APInt &Imm)
static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, EVT &VT, bool is128Bits, NEONModImmType type)
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
SDNode * getNode() const
get the SDNode which holds the desired result
bool isNormalLoad(const SDNode *N)
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
static EVT getFloatingPointVT(unsigned BitWidth)
Definition: ValueTypes.h:56
unsigned getOpcode() const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:154
static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, SDLoc dl)
Class for arbitrary precision integers.
Definition: APInt.h:75
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
EVT getValueType() const
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:136
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
SDValue ARMTargetLowering::LowerCall ( TargetLowering::CallLoweringInfo CLI,
SmallVectorImpl< SDValue > &  InVals 
) const
overrideprivatevirtual

LowerCall - Lowering a call into a callseq_start <- ARMISD:CALL <- callseq_end chain. Also add input and output parameter nodes.

Reimplemented from llvm::TargetLowering.

Definition at line 1390 of file ARMISelLowering.cpp.

1391  {
1392  SelectionDAG &DAG = CLI.DAG;
1393  SDLoc &dl = CLI.DL;
1395  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1397  SDValue Chain = CLI.Chain;
1398  SDValue Callee = CLI.Callee;
1399  bool &isTailCall = CLI.IsTailCall;
1401  bool doesNotRet = CLI.DoesNotReturn;
1402  bool isVarArg = CLI.IsVarArg;
1403 
1404  MachineFunction &MF = DAG.getMachineFunction();
1405  bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1406  bool isThisReturn = false;
1407  bool isSibCall = false;
1408 
1409  // Disable tail calls if they're not supported.
1411  isTailCall = false;
1412 
1413  if (isTailCall) {
1414  // Check if it's really possible to do a tail call.
1415  isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1416  isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1417  Outs, OutVals, Ins, DAG);
1418  if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
1419  report_fatal_error("failed to perform tail call elimination on a call "
1420  "site marked musttail");
1421  // We don't support GuaranteedTailCallOpt for ARM, only automatically
1422  // detected sibcalls.
1423  if (isTailCall) {
1424  ++NumTailCalls;
1425  isSibCall = true;
1426  }
1427  }
1428 
1429  // Analyze operands of the call, assigning locations to each operand.
1431  ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1432  getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1433  CCInfo.AnalyzeCallOperands(Outs,
1434  CCAssignFnForNode(CallConv, /* Return*/ false,
1435  isVarArg));
1436 
1437  // Get a count of how many bytes are to be pushed on the stack.
1438  unsigned NumBytes = CCInfo.getNextStackOffset();
1439 
1440  // For tail calls, memory operands are available in our caller's stack.
1441  if (isSibCall)
1442  NumBytes = 0;
1443 
1444  // Adjust the stack pointer for the new arguments...
1445  // These operations are automatically eliminated by the prolog/epilog pass
1446  if (!isSibCall)
1447  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1448  dl);
1449 
1450  SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1451 
1452  RegsToPassVector RegsToPass;
1453  SmallVector<SDValue, 8> MemOpChains;
1454 
1455  // Walk the register/memloc assignments, inserting copies/loads. In the case
1456  // of tail call optimization, arguments are handled later.
1457  for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1458  i != e;
1459  ++i, ++realArgIdx) {
1460  CCValAssign &VA = ArgLocs[i];
1461  SDValue Arg = OutVals[realArgIdx];
1462  ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1463  bool isByVal = Flags.isByVal();
1464 
1465  // Promote the value if needed.
1466  switch (VA.getLocInfo()) {
1467  default: llvm_unreachable("Unknown loc info!");
1468  case CCValAssign::Full: break;
1469  case CCValAssign::SExt:
1470  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1471  break;
1472  case CCValAssign::ZExt:
1473  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1474  break;
1475  case CCValAssign::AExt:
1476  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1477  break;
1478  case CCValAssign::BCvt:
1479  Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1480  break;
1481  }
1482 
1483  // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1484  if (VA.needsCustom()) {
1485  if (VA.getLocVT() == MVT::v2f64) {
1486  SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1487  DAG.getConstant(0, MVT::i32));
1488  SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1489  DAG.getConstant(1, MVT::i32));
1490 
1491  PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1492  VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1493 
1494  VA = ArgLocs[++i]; // skip ahead to next loc
1495  if (VA.isRegLoc()) {
1496  PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1497  VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1498  } else {
1499  assert(VA.isMemLoc());
1500 
1501  MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1502  dl, DAG, VA, Flags));
1503  }
1504  } else {
1505  PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1506  StackPtr, MemOpChains, Flags);
1507  }
1508  } else if (VA.isRegLoc()) {
1509  if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1510  assert(VA.getLocVT() == MVT::i32 &&
1511  "unexpected calling convention register assignment");
1512  assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1513  "unexpected use of 'returned'");
1514  isThisReturn = true;
1515  }
1516  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1517  } else if (isByVal) {
1518  assert(VA.isMemLoc());
1519  unsigned offset = 0;
1520 
1521  // True if this byval aggregate will be split between registers
1522  // and memory.
1523  unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1524  unsigned CurByValIdx = CCInfo.getInRegsParamsProceed();
1525 
1526  if (CurByValIdx < ByValArgsCount) {
1527 
1528  unsigned RegBegin, RegEnd;
1529  CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1530 
1531  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1532  unsigned int i, j;
1533  for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1534  SDValue Const = DAG.getConstant(4*i, MVT::i32);
1535  SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1536  SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1538  false, false, false,
1539  DAG.InferPtrAlignment(AddArg));
1540  MemOpChains.push_back(Load.getValue(1));
1541  RegsToPass.push_back(std::make_pair(j, Load));
1542  }
1543 
1544  // If parameter size outsides register area, "offset" value
1545  // helps us to calculate stack slot for remained part properly.
1546  offset = RegEnd - RegBegin;
1547 
1548  CCInfo.nextInRegsParam();
1549  }
1550 
1551  if (Flags.getByValSize() > 4*offset) {
1552  unsigned LocMemOffset = VA.getLocMemOffset();
1553  SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1554  SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1555  StkPtrOff);
1556  SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1557  SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1558  SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1559  MVT::i32);
1560  SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1561 
1562  SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1563  SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1564  MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1565  Ops));
1566  }
1567  } else if (!isSibCall) {
1568  assert(VA.isMemLoc());
1569 
1570  MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1571  dl, DAG, VA, Flags));
1572  }
1573  }
1574 
1575  if (!MemOpChains.empty())
1576  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1577 
1578  // Build a sequence of copy-to-reg nodes chained together with token chain
1579  // and flag operands which copy the outgoing args into the appropriate regs.
1580  SDValue InFlag;
1581  // Tail call byval lowering might overwrite argument registers so in case of
1582  // tail call optimization the copies to registers are lowered later.
1583  if (!isTailCall)
1584  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1585  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1586  RegsToPass[i].second, InFlag);
1587  InFlag = Chain.getValue(1);
1588  }
1589 
1590  // For tail calls lower the arguments to the 'real' stack slot.
1591  if (isTailCall) {
1592  // Force all the incoming stack arguments to be loaded from the stack
1593  // before any new outgoing arguments are stored to the stack, because the
1594  // outgoing stack slots may alias the incoming argument stack slots, and
1595  // the alias isn't otherwise explicit. This is slightly more conservative
1596  // than necessary, because it means that each store effectively depends
1597  // on every argument instead of just those arguments it would clobber.
1598 
1599  // Do not flag preceding copytoreg stuff together with the following stuff.
1600  InFlag = SDValue();
1601  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1602  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1603  RegsToPass[i].second, InFlag);
1604  InFlag = Chain.getValue(1);
1605  }
1606  InFlag = SDValue();
1607  }
1608 
1609  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1610  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1611  // node so that legalize doesn't hack it.
1612  bool isDirect = false;
1613  bool isARMFunc = false;
1614  bool isLocalARMFunc = false;
1616 
1617  if (EnableARMLongCalls) {
1620  "long-calls with non-static relocation model!");
1621  // Handle a global address or an external symbol. If it's not one of
1622  // those, the target's already in a register, so we don't need to do
1623  // anything extra.
1624  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1625  const GlobalValue *GV = G->getGlobal();
1626  // Create a constant pool entry for the callee address
1627  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1628  ARMConstantPoolValue *CPV =
1629  ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1630 
1631  // Get the address of the callee into a register
1632  SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1633  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1634  Callee = DAG.getLoad(getPointerTy(), dl,
1635  DAG.getEntryNode(), CPAddr,
1637  false, false, false, 0);
1638  } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1639  const char *Sym = S->getSymbol();
1640 
1641  // Create a constant pool entry for the callee address
1642  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1643  ARMConstantPoolValue *CPV =
1645  ARMPCLabelIndex, 0);
1646  // Get the address of the callee into a register
1647  SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1648  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1649  Callee = DAG.getLoad(getPointerTy(), dl,
1650  DAG.getEntryNode(), CPAddr,
1652  false, false, false, 0);
1653  }
1654  } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1655  const GlobalValue *GV = G->getGlobal();
1656  isDirect = true;
1657  bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1658  bool isStub = (isExt && Subtarget->isTargetMachO()) &&
1660  isARMFunc = !Subtarget->isThumb() || isStub;
1661  // ARM call to a local ARM function is predicable.
1662  isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1663  // tBX takes a register source operand.
1664  if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1665  assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1666  Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
1667  DAG.getTargetGlobalAddress(GV, dl, getPointerTy()));
1668  } else if (Subtarget->isTargetCOFF()) {
1670  "Windows is the only supported COFF target");
1671  unsigned TargetFlags = GV->hasDLLImportStorageClass()
1674  Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), /*Offset=*/0,
1675  TargetFlags);
1676  if (GV->hasDLLImportStorageClass())
1677  Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1679  Callee), MachinePointerInfo::getGOT(),
1680  false, false, false, 0);
1681  } else {
1682  // On ELF targets for PIC code, direct calls should go through the PLT
1683  unsigned OpFlags = 0;
1684  if (Subtarget->isTargetELF() &&
1686  OpFlags = ARMII::MO_PLT;
1687  Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1688  }
1689  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1690  isDirect = true;
1691  bool isStub = Subtarget->isTargetMachO() &&
1693  isARMFunc = !Subtarget->isThumb() || isStub;
1694  // tBX takes a register source operand.
1695  const char *Sym = S->getSymbol();
1696  if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1697  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1698  ARMConstantPoolValue *CPV =
1700  ARMPCLabelIndex, 4);
1701  SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1702  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1703  Callee = DAG.getLoad(getPointerTy(), dl,
1704  DAG.getEntryNode(), CPAddr,
1706  false, false, false, 0);
1707  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1708  Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1709  getPointerTy(), Callee, PICLabel);
1710  } else {
1711  unsigned OpFlags = 0;
1712  // On ELF targets for PIC code, direct calls should go through the PLT
1713  if (Subtarget->isTargetELF() &&
1715  OpFlags = ARMII::MO_PLT;
1716  Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1717  }
1718  }
1719 
1720  // FIXME: handle tail calls differently.
1721  unsigned CallOpc;
1722  bool HasMinSizeAttr = MF.getFunction()->getAttributes().hasAttribute(
1724  if (Subtarget->isThumb()) {
1725  if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1726  CallOpc = ARMISD::CALL_NOLINK;
1727  else
1728  CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1729  } else {
1730  if (!isDirect && !Subtarget->hasV5TOps())
1731  CallOpc = ARMISD::CALL_NOLINK;
1732  else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1733  // Emit regular call when code size is the priority
1734  !HasMinSizeAttr)
1735  // "mov lr, pc; b _foo" to avoid confusing the RSP
1736  CallOpc = ARMISD::CALL_NOLINK;
1737  else
1738  CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1739  }
1740 
1741  std::vector<SDValue> Ops;
1742  Ops.push_back(Chain);
1743  Ops.push_back(Callee);
1744 
1745  // Add argument registers to the end of the list so that they are known live
1746  // into the call.
1747  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1748  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1749  RegsToPass[i].second.getValueType()));
1750 
1751  // Add a register mask operand representing the call-preserved registers.
1752  if (!isTailCall) {
1753  const uint32_t *Mask;
1755  const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo*>(TRI);
1756  if (isThisReturn) {
1757  // For 'this' returns, use the R0-preserving mask if applicable
1758  Mask = ARI->getThisReturnPreservedMask(CallConv);
1759  if (!Mask) {
1760  // Set isThisReturn to false if the calling convention is not one that
1761  // allows 'returned' to be modeled in this way, so LowerCallResult does
1762  // not try to pass 'this' straight through
1763  isThisReturn = false;
1764  Mask = ARI->getCallPreservedMask(CallConv);
1765  }
1766  } else
1767  Mask = ARI->getCallPreservedMask(CallConv);
1768 
1769  assert(Mask && "Missing call preserved mask for calling convention");
1770  Ops.push_back(DAG.getRegisterMask(Mask));
1771  }
1772 
1773  if (InFlag.getNode())
1774  Ops.push_back(InFlag);
1775 
1776  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1777  if (isTailCall)
1778  return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
1779 
1780  // Returns a chain and a flag for retval copy to use.
1781  Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
1782  InFlag = Chain.getValue(1);
1783 
1784  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1785  DAG.getIntPtrConstant(0, true), InFlag, dl);
1786  if (!Ins.empty())
1787  InFlag = Chain.getValue(1);
1788 
1789  // Handle result values, copying them out of physregs into vregs that we
1790  // return.
1791  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1792  InVals, isThisReturn,
1793  isThisReturn ? OutVals[0] : SDValue());
1794 }
SDValue getValue(unsigned R) const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Definition: SelectionDAG.h:612
Reloc::Model getRelocationModel() const
LocInfo getLocInfo() const
const TargetMachine & getTargetMachine() const
unsigned InferPtrAlignment(SDValue Ptr) const
static cl::opt< bool > ARMInterworking("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))
unsigned getByValSize() const
const Function * getFunction() const
static MachinePointerInfo getConstantPool()
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
bool isRegLoc() const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
const uint32_t * getCallPreservedMask(CallingConv::ID) const override
bool isTargetELF() const
Definition: ARMSubtarget.h:354
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
bool isThumb() const
Definition: ARMSubtarget.h:400
#define G(x, y, z)
Definition: MD5.cpp:52
SmallVector< ISD::InputArg, 32 > Ins
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Definition: SelectionDAG.h:603
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
LowerMemOpCallTo - Store the argument to the stack.
unsigned getLocReg() const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
bool isTargetCOFF() const
Definition: ARMSubtarget.h:353
SDValue getRegisterMask(const uint32_t *RegMask)
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Definition: Function.h:305
bool isTargetMachO() const
Definition: ARMSubtarget.h:355
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< std::pair< unsigned, SDValue >, 8 > RegsToPassVector
static bool isWeakForLinker(LinkageTypes Linkage)
Definition: GlobalValue.h:235
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
bool supportsTailCall() const
Definition: ARMSubtarget.h:412
MVT getLocVT() const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
bool needsCustom() const
unsigned getByValAlign() const
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:450
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:148
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
const ARMSubtarget * Subtarget
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
static ARMConstantPoolSymbol * Create(LLVMContext &C, const char *s, unsigned ID, unsigned char PCAdj)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
bool isMemLoc() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl< SDValue > &MemOpChains, ISD::ArgFlagsTy Flags) const
static MachinePointerInfo getGOT()
SmallVector< SDValue, 32 > OutVals
CCAssignFn * CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const
bool isDeclaration() const
Definition: Globals.cpp:113
bool hasV5TOps() const
Definition: ARMSubtarget.h:286
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
const TargetMachine & getTarget() const
virtual const TargetRegisterInfo * getRegisterInfo() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
cl::opt< bool > EnableARMLongCalls("arm-long-calls", cl::Hidden, cl::desc("Generate calls via indirect call instructions"), cl::init(false))
const uint32_t * getThisReturnPreservedMask(CallingConv::ID) const
bool hasRAS() const
Definition: ARMSubtarget.h:336
SDValue getRegister(unsigned Reg, EVT VT)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
unsigned getLocMemOffset() const
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
bool isTargetWindows() const
Definition: ARMSubtarget.h:351
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
Function must be optimized for size first.
Definition: Attributes.h:79
SDValue ARMTargetLowering::LowerCallResult ( SDValue  Chain,
SDValue  InFlag,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals,
bool  isThisReturn,
SDValue  ThisVal 
) const
private

LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate physical registers.

Definition at line 1261 of file ARMISelLowering.cpp.

1266  {
1267 
1268  // Assign locations to each value returned by this call.
1270  ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1271  getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1272  CCInfo.AnalyzeCallResult(Ins,
1273  CCAssignFnForNode(CallConv, /* Return*/ true,
1274  isVarArg));
1275 
1276  // Copy all of the result registers out of their specified physreg.
1277  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1278  CCValAssign VA = RVLocs[i];
1279 
1280  // Pass 'this' value directly from the argument to return value, to avoid
1281  // reg unit interference
1282  if (i == 0 && isThisReturn) {
1283  assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1284  "unexpected return calling convention register assignment");
1285  InVals.push_back(ThisVal);
1286  continue;
1287  }
1288 
1289  SDValue Val;
1290  if (VA.needsCustom()) {
1291  // Handle f64 or half of a v2f64.
1292  SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1293  InFlag);
1294  Chain = Lo.getValue(1);
1295  InFlag = Lo.getValue(2);
1296  VA = RVLocs[++i]; // skip ahead to next loc
1297  SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1298  InFlag);
1299  Chain = Hi.getValue(1);
1300  InFlag = Hi.getValue(2);
1301  if (!Subtarget->isLittle())
1302  std::swap (Lo, Hi);
1303  Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1304 
1305  if (VA.getLocVT() == MVT::v2f64) {
1306  SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1307  Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1308  DAG.getConstant(0, MVT::i32));
1309 
1310  VA = RVLocs[++i]; // skip ahead to next loc
1311  Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1312  Chain = Lo.getValue(1);
1313  InFlag = Lo.getValue(2);
1314  VA = RVLocs[++i]; // skip ahead to next loc
1315  Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1316  Chain = Hi.getValue(1);
1317  InFlag = Hi.getValue(2);
1318  if (!Subtarget->isLittle())
1319  std::swap (Lo, Hi);
1320  Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1321  Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1322  DAG.getConstant(1, MVT::i32));
1323  }
1324  } else {
1325  Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1326  InFlag);
1327  Chain = Val.getValue(1);
1328  InFlag = Val.getValue(2);
1329  }
1330 
1331  switch (VA.getLocInfo()) {
1332  default: llvm_unreachable("Unknown loc info!");
1333  case CCValAssign::Full: break;
1334  case CCValAssign::BCvt:
1335  Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1336  break;
1337  }
1338 
1339  InVals.push_back(Val);
1340  }
1341 
1342  return Chain;
1343 }
SDValue getValue(unsigned R) const
MVT getValVT() const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
LocInfo getLocInfo() const
const TargetMachine & getTargetMachine() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
bool isLittle() const
Definition: ARMSubtarget.h:420
unsigned getLocReg() const
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
assert(Globals.size() > 1)
MVT getLocVT() const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
bool needsCustom() const
CCValAssign - Represent assignment of one arg/retval to a location.
const ARMSubtarget * Subtarget
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
CCAssignFn * CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
std::pair< SDValue, SDValue > TargetLowering::LowerCallTo ( TargetLowering::CallLoweringInfo CLI) const
inherited

This function lowers an abstract call to a function into an actual call. This returns a pair of operands. The first element is the return value for the function (if RetTy is not VoidTy). The second element is the outgoing token chain. It calls LowerCall to do the actual lowering.

TargetLowering::LowerCallTo - This is the default LowerCallTo implementation, which just calls LowerCall. FIXME: When all targets are migrated to using LowerCall, this hook should be integrated into SDISel.

Definition at line 7072 of file SelectionDAGBuilder.cpp.

7072  {
7073  // Handle the incoming return values from the call.
7074  CLI.Ins.clear();
7075  Type *OrigRetTy = CLI.RetTy;
7076  SmallVector<EVT, 4> RetTys;
7077  SmallVector<uint64_t, 4> Offsets;
7078  ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7079 
7081  GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7082 
7083  bool CanLowerReturn =
7084  this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7085  CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7086 
7087  SDValue DemoteStackSlot;
7088  int DemoteStackIdx = -100;
7089  if (!CanLowerReturn) {
7090  // FIXME: equivalent assert?
7091  // assert(!CS.hasInAllocaArgument() &&
7092  // "sret demotion is incompatible with inalloca");
7093  uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7094  unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7096  DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7097  Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7098 
7099  DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7100  ArgListEntry Entry;
7101  Entry.Node = DemoteStackSlot;
7102  Entry.Ty = StackSlotPtrType;
7103  Entry.isSExt = false;
7104  Entry.isZExt = false;
7105  Entry.isInReg = false;
7106  Entry.isSRet = true;
7107  Entry.isNest = false;
7108  Entry.isByVal = false;
7109  Entry.isReturned = false;
7110  Entry.Alignment = Align;
7111  CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7112  CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7113  } else {
7114  for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7115  EVT VT = RetTys[I];
7116  MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7117  unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7118  for (unsigned i = 0; i != NumRegs; ++i) {
7120  MyFlags.VT = RegisterVT;
7121  MyFlags.ArgVT = VT;
7122  MyFlags.Used = CLI.IsReturnValueUsed;
7123  if (CLI.RetSExt)
7124  MyFlags.Flags.setSExt();
7125  if (CLI.RetZExt)
7126  MyFlags.Flags.setZExt();
7127  if (CLI.IsInReg)
7128  MyFlags.Flags.setInReg();
7129  CLI.Ins.push_back(MyFlags);
7130  }
7131  }
7132  }
7133 
7134  // Handle all of the outgoing arguments.
7135  CLI.Outs.clear();
7136  CLI.OutVals.clear();
7137  ArgListTy &Args = CLI.getArgs();
7138  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7139  SmallVector<EVT, 4> ValueVTs;
7140  ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7141  Type *FinalType = Args[i].Ty;
7142  if (Args[i].isByVal)
7143  FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7144  bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7145  FinalType, CLI.CallConv, CLI.IsVarArg);
7146  for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7147  ++Value) {
7148  EVT VT = ValueVTs[Value];
7149  Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7150  SDValue Op = SDValue(Args[i].Node.getNode(),
7151  Args[i].Node.getResNo() + Value);
7153  unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7154 
7155  if (Args[i].isZExt)
7156  Flags.setZExt();
7157  if (Args[i].isSExt)
7158  Flags.setSExt();
7159  if (Args[i].isInReg)
7160  Flags.setInReg();
7161  if (Args[i].isSRet)
7162  Flags.setSRet();
7163  if (Args[i].isByVal)
7164  Flags.setByVal();
7165  if (Args[i].isInAlloca) {
7166  Flags.setInAlloca();
7167  // Set the byval flag for CCAssignFn callbacks that don't know about
7168  // inalloca. This way we can know how many bytes we should've allocated
7169  // and how many bytes a callee cleanup function will pop. If we port
7170  // inalloca to more targets, we'll have to add custom inalloca handling
7171  // in the various CC lowering callbacks.
7172  Flags.setByVal();
7173  }
7174  if (Args[i].isByVal || Args[i].isInAlloca) {
7175  PointerType *Ty = cast<PointerType>(Args[i].Ty);
7176  Type *ElementTy = Ty->getElementType();
7177  Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7178  // For ByVal, alignment should come from FE. BE will guess if this
7179  // info is not there but there are cases it cannot get right.
7180  unsigned FrameAlign;
7181  if (Args[i].Alignment)
7182  FrameAlign = Args[i].Alignment;
7183  else
7184  FrameAlign = getByValTypeAlignment(ElementTy);
7185  Flags.setByValAlign(FrameAlign);
7186  }
7187  if (Args[i].isNest)
7188  Flags.setNest();
7189  if (NeedsRegBlock)
7190  Flags.setInConsecutiveRegs();
7191  Flags.setOrigAlign(OriginalAlignment);
7192 
7193  MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7194  unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7195  SmallVector<SDValue, 4> Parts(NumParts);
7196  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7197 
7198  if (Args[i].isSExt)
7199  ExtendKind = ISD::SIGN_EXTEND;
7200  else if (Args[i].isZExt)
7201  ExtendKind = ISD::ZERO_EXTEND;
7202 
7203  // Conservatively only handle 'returned' on non-vectors for now
7204  if (Args[i].isReturned && !Op.getValueType().isVector()) {
7205  assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7206  "unexpected use of 'returned'");
7207  // Before passing 'returned' to the target lowering code, ensure that
7208  // either the register MVT and the actual EVT are the same size or that
7209  // the return value and argument are extended in the same way; in these
7210  // cases it's safe to pass the argument register value unchanged as the
7211  // return register value (although it's at the target's option whether
7212  // to do so)
7213  // TODO: allow code generation to take advantage of partially preserved
7214  // registers rather than clobbering the entire register when the
7215  // parameter extension method is not compatible with the return
7216  // extension method
7217  if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7218  (ExtendKind != ISD::ANY_EXTEND &&
7219  CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7220  Flags.setReturned();
7221  }
7222 
7223  getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7224  CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7225 
7226  for (unsigned j = 0; j != NumParts; ++j) {
7227  // if it isn't first piece, alignment must be 1
7228  ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7229  i < CLI.NumFixedArgs,
7230  i, j*Parts[j].getValueType().getStoreSize());
7231  if (NumParts > 1 && j == 0)
7232  MyFlags.Flags.setSplit();
7233  else if (j != 0)
7234  MyFlags.Flags.setOrigAlign(1);
7235 
7236  // Only mark the end at the last register of the last value.
7237  if (NeedsRegBlock && Value == NumValues - 1 && j == NumParts - 1)
7238  MyFlags.Flags.setInConsecutiveRegsLast();
7239 
7240  CLI.Outs.push_back(MyFlags);
7241  CLI.OutVals.push_back(Parts[j]);
7242  }
7243  }
7244  }
7245 
7246  SmallVector<SDValue, 4> InVals;
7247  CLI.Chain = LowerCall(CLI, InVals);
7248 
7249  // Verify that the target's LowerCall behaved as expected.
7250  assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7251  "LowerCall didn't return a valid chain!");
7252  assert((!CLI.IsTailCall || InVals.empty()) &&
7253  "LowerCall emitted a return value for a tail call!");
7254  assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7255  "LowerCall didn't emit the correct number of values!");
7256 
7257  // For a tail call, the return value is merely live-out and there aren't
7258  // any nodes in the DAG representing it. Return a special value to
7259  // indicate that a tail call has been emitted and no more Instructions
7260  // should be processed in the current block.
7261  if (CLI.IsTailCall) {
7262  CLI.DAG.setRoot(CLI.Chain);
7263  return std::make_pair(SDValue(), SDValue());
7264  }
7265 
7266  DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7267  assert(InVals[i].getNode() &&
7268  "LowerCall emitted a null value!");
7269  assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7270  "LowerCall emitted a value with the wrong type!");
7271  });
7272 
7273  SmallVector<SDValue, 4> ReturnValues;
7274  if (!CanLowerReturn) {
7275  // The instruction result is the result of loading from the
7276  // hidden sret parameter.
7277  SmallVector<EVT, 1> PVTs;
7278  Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7279 
7280  ComputeValueVTs(*this, PtrRetTy, PVTs);
7281  assert(PVTs.size() == 1 && "Pointers should fit in one register");
7282  EVT PtrVT = PVTs[0];
7283 
7284  unsigned NumValues = RetTys.size();
7285  ReturnValues.resize(NumValues);
7286  SmallVector<SDValue, 4> Chains(NumValues);
7287 
7288  for (unsigned i = 0; i < NumValues; ++i) {
7289  SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7290  CLI.DAG.getConstant(Offsets[i], PtrVT));
7291  SDValue L = CLI.DAG.getLoad(
7292  RetTys[i], CLI.DL, CLI.Chain, Add,
7293  MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7294  false, false, 1);
7295  ReturnValues[i] = L;
7296  Chains[i] = L.getValue(1);
7297  }
7298 
7299  CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7300  } else {
7301  // Collect the legal value parts into potentially illegal values
7302  // that correspond to the original function's return values.
7303  ISD::NodeType AssertOp = ISD::DELETED_NODE;
7304  if (CLI.RetSExt)
7305  AssertOp = ISD::AssertSext;
7306  else if (CLI.RetZExt)
7307  AssertOp = ISD::AssertZext;
7308  unsigned CurReg = 0;
7309  for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7310  EVT VT = RetTys[I];
7311  MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7312  unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7313 
7314  ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7315  NumRegs, RegisterVT, VT, nullptr,
7316  AssertOp));
7317  CurReg += NumRegs;
7318  }
7319 
7320  // For a function returning void, there is no return value. We can't create
7321  // such a node, so we just return a null return value in that case. In
7322  // that case, nothing will actually look at the value.
7323  if (ReturnValues.empty())
7324  return std::make_pair(SDValue(), CLI.Chain);
7325  }
7326 
7327  SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7328  CLI.DAG.getVTList(RetTys), ReturnValues);
7329  return std::make_pair(Res, CLI.Chain);
7330 }
void push_back(const T &Elt)
Definition: SmallVector.h:225
SDValue getValue(unsigned R) const
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
unsigned getPrefTypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:693
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
unsigned getSizeInBits() const
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
const SDValue & setRoot(SDValue N)
Definition: SelectionDAG.h:333
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
MyFlags
Definition: YAMLIOTest.cpp:502
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
SmallVector< ISD::InputArg, 32 > Ins
static int Value(bit_value_t V)
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
const DomTreeNodeT * Node
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SmallVector< ISD::OutputArg, 32 > Outs
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
void setOrigAlign(unsigned A)
Type * getElementType() const
Definition: DerivedTypes.h:319
SDNode * getNode() const
get the SDNode which holds the desired result
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI)
assert(Globals.size() > 1)
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:221
const DataLayout * getDataLayout() const
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual unsigned getByValTypeAlignment(Type *Ty) const
#define DEBUG(X)
std::vector< ArgListEntry > ArgListTy
unsigned getABITypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:683
static PointerType * getUnqual(Type *ElementType)
Definition: DerivedTypes.h:456
const char * Args[]
uint64_t getTypeAllocSize(Type *Ty) const
Definition: DataLayout.h:368
MachineFrameInfo * getFrameInfo()
static void getCopyToParts(SelectionDAG &DAG, SDLoc DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, ISD::NodeType ExtendKind=ISD::ANY_EXTEND)
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, ISD::NodeType AssertOp=ISD::DELETED_NODE)
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI)
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
SmallVector< SDValue, 32 > OutVals
void ComputeValueVTs(const TargetLowering &TLI, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
#define I(x, y, z)
Definition: MD5.cpp:54
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVM Value Representation.
Definition: Value.h:69
SDValue ARMTargetLowering::LowerConstantFP ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget ST 
) const
private

Definition at line 4561 of file ARMISelLowering.cpp.

4562  {
4563  if (!ST->hasVFP3())
4564  return SDValue();
4565 
4566  bool IsDouble = Op.getValueType() == MVT::f64;
4567  ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4568 
4569  // Try splatting with a VMOV.f32...
4570  APFloat FPVal = CFP->getValueAPF();
4571  int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4572 
4573  if (ImmVal != -1) {
4574  if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4575  // We have code in place to select a valid ConstantFP already, no need to
4576  // do any mangling.
4577  return Op;
4578  }
4579 
4580  // It's a float and we are trying to use NEON operations where
4581  // possible. Lower it to a splat followed by an extract.
4582  SDLoc DL(Op);
4583  SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4584  SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4585  NewVal);
4586  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4587  DAG.getConstant(0, MVT::i32));
4588  }
4589 
4590  // The rest of our options are NEON only, make sure that's allowed before
4591  // proceeding..
4592  if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4593  return SDValue();
4594 
4595  EVT VMovVT;
4596  uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4597 
4598  // It wouldn't really be worth bothering for doubles except for one very
4599  // important value, which does happen to match: 0.0. So make sure we don't do
4600  // anything stupid.
4601  if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4602  return SDValue();
4603 
4604  // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4605  SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4606  false, VMOVModImm);
4607  if (NewVal != SDValue()) {
4608  SDLoc DL(Op);
4609  SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4610  NewVal);
4611  if (IsDouble)
4612  return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4613 
4614  // It's a float: cast and extract a vector element.
4615  SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4616  VecConstant);
4617  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4618  DAG.getConstant(0, MVT::i32));
4619  }
4620 
4621  // Finally, try a VMVN.i32
4622  NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4623  false, VMVNModImm);
4624  if (NewVal != SDValue()) {
4625  SDLoc DL(Op);
4626  SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4627 
4628  if (IsDouble)
4629  return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4630 
4631  // It's a float: cast and extract a vector element.
4632  SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4633  VecConstant);
4634  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4635  DAG.getConstant(0, MVT::i32));
4636  }
4637 
4638  return SDValue();
4639 }
bool hasVFP3() const
Definition: ARMSubtarget.h:308
const DataLayout * DL
True if this is a little endian target.
bool hasNEON() const
Definition: ARMSubtarget.h:311
static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, EVT &VT, bool is128Bits, NEONModImmType type)
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
Definition: APFloat.h:122
static int getFP32Imm(const APInt &Imm)
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:315
const APFloat & getValueAPF() const
static int getFP64Imm(const APInt &Imm)
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
virtual const MCExpr* llvm::TargetLowering::LowerCustomJumpTableEntry ( const MachineJumpTableInfo ,
const MachineBasicBlock ,
unsigned  ,
MCContext  
) const
inlinevirtualinherited

Reimplemented in llvm::X86TargetLowering.

Definition at line 1894 of file TargetLowering.h.

1896  {
1897  llvm_unreachable("Need to implement this hook if target has custom JTIs");
1898  }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
SDValue ARMTargetLowering::LowerDivRem ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 10561 of file ARMISelLowering.cpp.

10561  {
10562  assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
10563  unsigned Opcode = Op->getOpcode();
10564  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
10565  "Invalid opcode for Div/Rem lowering");
10566  bool isSigned = (Opcode == ISD::SDIVREM);
10567  EVT VT = Op->getValueType(0);
10568  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
10569 
10570  RTLIB::Libcall LC;
10571  switch (VT.getSimpleVT().SimpleTy) {
10572  default: llvm_unreachable("Unexpected request for libcall!");
10573  case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
10574  case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
10575  case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
10576  case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
10577  }
10578 
10579  SDValue InChain = DAG.getEntryNode();
10580 
10583  for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
10584  EVT ArgVT = Op->getOperand(i).getValueType();
10585  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10586  Entry.Node = Op->getOperand(i);
10587  Entry.Ty = ArgTy;
10588  Entry.isSExt = isSigned;
10589  Entry.isZExt = !isSigned;
10590  Args.push_back(Entry);
10591  }
10592 
10593  SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
10594  getPointerTy());
10595 
10596  Type *RetTy = (Type*)StructType::get(Ty, Ty, NULL);
10597 
10598  SDLoc dl(Op);
10600  CLI.setDebugLoc(dl).setChain(InChain)
10601  .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
10602  .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
10603 
10604  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
10605  return CallInfo.first;
10606 }
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
unsigned getOpcode() const
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
unsigned getNumOperands() const
const SDValue & getOperand(unsigned Num) const
SDValue getExternalSymbol(const char *Sym, EVT VT)
bool isTargetAEABI() const
Definition: ARMSubtarget.h:364
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
SimpleValueType SimpleTy
virtual MVT getPointerTy(uint32_t=0) const
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
assert(Globals.size() > 1)
std::vector< ArgListEntry > ArgListTy
const char * Args[]
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
Definition: Type.cpp:399
const ARMSubtarget * Subtarget
EVT getValueType() const
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
MVT getSimpleVT() const
Definition: ValueTypes.h:204
SDValue ARMTargetLowering::LowerDYNAMIC_STACKALLOC ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 10609 of file ARMISelLowering.cpp.

10609  {
10610  assert(Subtarget->isTargetWindows() && "unsupported target platform");
10611  SDLoc DL(Op);
10612 
10613  // Get the inputs.
10614  SDValue Chain = Op.getOperand(0);
10615  SDValue Size = Op.getOperand(1);
10616 
10617  SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
10618  DAG.getConstant(2, MVT::i32));
10619 
10620  SDValue Flag;
10621  Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
10622  Flag = Chain.getValue(1);
10623 
10624  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10625  Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
10626 
10627  SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
10628  Chain = NewSP.getValue(1);
10629 
10630  SDValue Ops[2] = { NewSP, Chain };
10631  return DAG.getMergeValues(Ops, DL);
10632 }
SDValue getValue(unsigned R) const
#define R4(n)
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
getMergeValues - Create a MERGE_VALUES node from the given operands.
const DataLayout * DL
True if this is a little endian target.
SDVTList getVTList(EVT VT)
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
const ARMSubtarget * Subtarget
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
bool isTargetWindows() const
Definition: ARMSubtarget.h:351
SDValue ARMTargetLowering::LowerEH_SJLJ_LONGJMP ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2567 of file ARMISelLowering.cpp.

2567  {
2568  SDLoc dl(Op);
2569  return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2570  Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2571 }
const SDValue & getOperand(unsigned i) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue ARMTargetLowering::LowerEH_SJLJ_SETJMP ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2558 of file ARMISelLowering.cpp.

2558  {
2559  SDLoc dl(Op);
2560  SDValue Val = DAG.getConstant(0, MVT::i32);
2561  return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2562  DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2563  Op.getOperand(1), Val);
2564 }
SDVTList getVTList(EVT VT)
const SDValue & getOperand(unsigned i) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue ARMTargetLowering::LowerFCOPYSIGN ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3814 of file ARMISelLowering.cpp.

3814  {
3815  // Implement fcopysign with a fabs and a conditional fneg.
3816  SDValue Tmp0 = Op.getOperand(0);
3817  SDValue Tmp1 = Op.getOperand(1);
3818  SDLoc dl(Op);
3819  EVT VT = Op.getValueType();
3820  EVT SrcVT = Tmp1.getValueType();
3821  bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3822  Tmp0.getOpcode() == ARMISD::VMOVDRR;
3823  bool UseNEON = !InGPR && Subtarget->hasNEON();
3824 
3825  if (UseNEON) {
3826  // Use VBSL to copy the sign bit.
3827  unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3828  SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3829  DAG.getTargetConstant(EncodedVal, MVT::i32));
3830  EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3831  if (VT == MVT::f64)
3832  Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3833  DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3834  DAG.getConstant(32, MVT::i32));
3835  else /*if (VT == MVT::f32)*/
3836  Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3837  if (SrcVT == MVT::f32) {
3838  Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3839  if (VT == MVT::f64)
3840  Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3841  DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3842  DAG.getConstant(32, MVT::i32));
3843  } else if (VT == MVT::f32)
3844  Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3845  DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3846  DAG.getConstant(32, MVT::i32));
3847  Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3848  Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3849 
3851  MVT::i32);
3852  AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3853  SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3854  DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3855 
3856  SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3857  DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3858  DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3859  if (VT == MVT::f32) {
3860  Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3861  Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3862  DAG.getConstant(0, MVT::i32));
3863  } else {
3864  Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3865  }
3866 
3867  return Res;
3868  }
3869 
3870  // Bitcast operand 1 to i32.
3871  if (SrcVT == MVT::f64)
3872  Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3873  Tmp1).getValue(1);
3874  Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3875 
3876  // Or in the signbit with integer operations.
3877  SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3878  SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3879  Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3880  if (VT == MVT::f32) {
3881  Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3882  DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3883  return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3884  DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3885  }
3886 
3887  // f64: Or the high part with signbit and then combine two parts.
3888  Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3889  Tmp0);
3890  SDValue Lo = Tmp0.getValue(0);
3891  SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3892  Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3893  return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3894 }
SDValue getValue(unsigned R) const
class llvm::X86Disassembler::DisassemblerTables xff
SDVTList getVTList(EVT VT)
static unsigned createNEONModImm(unsigned OpCmode, unsigned Val)
bool hasNEON() const
Definition: ARMSubtarget.h:311
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
const ARMSubtarget * Subtarget
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue ARMTargetLowering::LowerFLT_ROUNDS_ ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 4081 of file ARMISelLowering.cpp.

4082  {
4083  // The rounding mode is in bits 23:22 of the FPSCR.
4084  // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
4085  // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4086  // so that the shift + and get folded into a bitfield extract.
4087  SDLoc dl(Op);
4089  DAG.getConstant(Intrinsic::arm_get_fpscr,
4090  MVT::i32));
4091  SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
4092  DAG.getConstant(1U << 22, MVT::i32));
4093  SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
4094  DAG.getConstant(22, MVT::i32));
4095  return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
4096  DAG.getConstant(3, MVT::i32));
4097 }
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue ARMTargetLowering::LowerFormalArguments ( SDValue  Chain,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2916 of file ARMISelLowering.cpp.

2922  {
2923  MachineFunction &MF = DAG.getMachineFunction();
2924  MachineFrameInfo *MFI = MF.getFrameInfo();
2925 
2927 
2928  // Assign locations to all of the incoming arguments.
2930  ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2931  getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2932  CCInfo.AnalyzeFormalArguments(Ins,
2933  CCAssignFnForNode(CallConv, /* Return*/ false,
2934  isVarArg));
2935 
2936  SmallVector<SDValue, 16> ArgValues;
2937  int lastInsIndex = -1;
2938  SDValue ArgValue;
2939  Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2940  unsigned CurArgIdx = 0;
2941 
2942  // Initially ArgRegsSaveSize is zero.
2943  // Then we increase this value each time we meet byval parameter.
2944  // We also increase this value in case of varargs function.
2945  AFI->setArgRegsSaveSize(0);
2946 
2947  unsigned ByValStoreOffset = 0;
2948  unsigned TotalArgRegsSaveSize = 0;
2949  unsigned ArgRegsSaveSizeMaxAlign = 4;
2950 
2951  // Calculate the amount of stack space that we need to allocate to store
2952  // byval and variadic arguments that are passed in registers.
2953  // We need to know this before we allocate the first byval or variadic
2954  // argument, as they will be allocated a stack slot below the CFA (Canonical
2955  // Frame Address, the stack pointer at entry to the function).
2956  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2957  CCValAssign &VA = ArgLocs[i];
2958  if (VA.isMemLoc()) {
2959  int index = VA.getValNo();
2960  if (index != lastInsIndex) {
2961  ISD::ArgFlagsTy Flags = Ins[index].Flags;
2962  if (Flags.isByVal()) {
2963  unsigned ExtraArgRegsSize;
2964  unsigned ExtraArgRegsSaveSize;
2965  computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsProceed(),
2966  Flags.getByValSize(),
2967  ExtraArgRegsSize, ExtraArgRegsSaveSize);
2968 
2969  TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
2970  if (Flags.getByValAlign() > ArgRegsSaveSizeMaxAlign)
2971  ArgRegsSaveSizeMaxAlign = Flags.getByValAlign();
2972  CCInfo.nextInRegsParam();
2973  }
2974  lastInsIndex = index;
2975  }
2976  }
2977  }
2978  CCInfo.rewindByValRegsInfo();
2979  lastInsIndex = -1;
2980  if (isVarArg) {
2981  unsigned ExtraArgRegsSize;
2982  unsigned ExtraArgRegsSaveSize;
2983  computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsCount(), 0,
2984  ExtraArgRegsSize, ExtraArgRegsSaveSize);
2985  TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
2986  }
2987  // If the arg regs save area contains N-byte aligned values, the
2988  // bottom of it must be at least N-byte aligned.
2989  TotalArgRegsSaveSize = RoundUpToAlignment(TotalArgRegsSaveSize, ArgRegsSaveSizeMaxAlign);
2990  TotalArgRegsSaveSize = std::min(TotalArgRegsSaveSize, 16U);
2991 
2992  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2993  CCValAssign &VA = ArgLocs[i];
2994  std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2995  CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
2996  // Arguments stored in registers.
2997  if (VA.isRegLoc()) {
2998  EVT RegVT = VA.getLocVT();
2999 
3000  if (VA.needsCustom()) {
3001  // f64 and vector types are split up into multiple registers or
3002  // combinations of registers and stack slots.
3003  if (VA.getLocVT() == MVT::v2f64) {
3004  SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3005  Chain, DAG, dl);
3006  VA = ArgLocs[++i]; // skip ahead to next loc
3007  SDValue ArgValue2;
3008  if (VA.isMemLoc()) {
3009  int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3010  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3011  ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3013  false, false, false, 0);
3014  } else {
3015  ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3016  Chain, DAG, dl);
3017  }
3018  ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3019  ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3020  ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
3021  ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3022  ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
3023  } else
3024  ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3025 
3026  } else {
3027  const TargetRegisterClass *RC;
3028 
3029  if (RegVT == MVT::f32)
3030  RC = &ARM::SPRRegClass;
3031  else if (RegVT == MVT::f64)
3032  RC = &ARM::DPRRegClass;
3033  else if (RegVT == MVT::v2f64)
3034  RC = &ARM::QPRRegClass;
3035  else if (RegVT == MVT::i32)
3036  RC = AFI->isThumb1OnlyFunction() ?
3037  (const TargetRegisterClass*)&ARM::tGPRRegClass :
3038  (const TargetRegisterClass*)&ARM::GPRRegClass;
3039  else
3040  llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3041 
3042  // Transform the arguments in physical registers into virtual ones.
3043  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3044  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3045  }
3046 
3047  // If this is an 8 or 16-bit value, it is really passed promoted
3048  // to 32 bits. Insert an assert[sz]ext to capture this, then
3049  // truncate to the right size.
3050  switch (VA.getLocInfo()) {
3051  default: llvm_unreachable("Unknown loc info!");
3052  case CCValAssign::Full: break;
3053  case CCValAssign::BCvt:
3054  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3055  break;
3056  case CCValAssign::SExt:
3057  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3058  DAG.getValueType(VA.getValVT()));
3059  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3060  break;
3061  case CCValAssign::ZExt:
3062  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3063  DAG.getValueType(VA.getValVT()));
3064  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3065  break;
3066  }
3067 
3068  InVals.push_back(ArgValue);
3069 
3070  } else { // VA.isRegLoc()
3071 
3072  // sanity check
3073  assert(VA.isMemLoc());
3074  assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3075 
3076  int index = ArgLocs[i].getValNo();
3077 
3078  // Some Ins[] entries become multiple ArgLoc[] entries.
3079  // Process them only once.
3080  if (index != lastInsIndex)
3081  {
3082  ISD::ArgFlagsTy Flags = Ins[index].Flags;
3083  // FIXME: For now, all byval parameter objects are marked mutable.
3084  // This can be changed with more analysis.
3085  // In case of tail call optimization mark all arguments mutable.
3086  // Since they could be overwritten by lowering of arguments in case of
3087  // a tail call.
3088  if (Flags.isByVal()) {
3089  unsigned CurByValIndex = CCInfo.getInRegsParamsProceed();
3090 
3091  ByValStoreOffset = RoundUpToAlignment(ByValStoreOffset, Flags.getByValAlign());
3092  int FrameIndex = StoreByValRegs(
3093  CCInfo, DAG, dl, Chain, CurOrigArg,
3094  CurByValIndex,
3095  Ins[VA.getValNo()].PartOffset,
3096  VA.getLocMemOffset(),
3097  Flags.getByValSize(),
3098  true /*force mutable frames*/,
3099  ByValStoreOffset,
3100  TotalArgRegsSaveSize);
3101  ByValStoreOffset += Flags.getByValSize();
3102  ByValStoreOffset = std::min(ByValStoreOffset, 16U);
3103  InVals.push_back(DAG.getFrameIndex(FrameIndex, getPointerTy()));
3104  CCInfo.nextInRegsParam();
3105  } else {
3106  unsigned FIOffset = VA.getLocMemOffset();
3107  int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3108  FIOffset, true);
3109 
3110  // Create load nodes to retrieve arguments from the stack.
3111  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3112  InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3114  false, false, false, 0));
3115  }
3116  lastInsIndex = index;
3117  }
3118  }
3119  }
3120 
3121  // varargs
3122  if (isVarArg)
3123  VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3124  CCInfo.getNextStackOffset(),
3125  TotalArgRegsSaveSize);
3126 
3127  AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3128 
3129  return Chain;
3130 }
int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, const Value *OrigArg, unsigned InRegsParamRecordIdx, unsigned OffsetFromOrigArg, unsigned ArgOffset, unsigned ArgSize, bool ForceMutable, unsigned ByValStoreOffset, unsigned TotalArgRegsSaveSize) const
MVT getValVT() const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
LocInfo getLocInfo() const
const TargetMachine & getTargetMachine() const
SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, SDLoc dl) const
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
unsigned getSizeInBits() const
unsigned getByValSize() const
const Function * getFunction() const
unsigned getValNo() const
bool isRegLoc() const
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
static void advance(T &it, size_t Val)
Reg
All possible values of the reg field in the ModR/M byte.
Abstract Stack Frame Information.
virtual MVT getPointerTy(uint32_t=0) const
unsigned getLocReg() const
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
assert(Globals.size() > 1)
MVT getLocVT() const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
arg_iterator arg_begin()
Definition: Function.h:417
void computeRegArea(CCState &CCInfo, MachineFunction &MF, unsigned InRegsParamRecordIdx, unsigned ArgSize, unsigned &ArgRegsSize, unsigned &ArgRegsSaveSize) const
bool needsCustom() const
unsigned getByValAlign() const
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
MachineFrameInfo * getFrameInfo()
bool isMemLoc() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align)
Definition: MathExtras.h:593
void setArgumentStackSize(unsigned size)
CCAssignFn * CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const
void setArgRegsSaveSize(unsigned s)
void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, unsigned ArgOffset, unsigned TotalArgRegsSaveSize, bool ForceMutable=false) const
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getValueType(EVT)
unsigned getLocMemOffset() const
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue ARMTargetLowering::LowerFRAMEADDR ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3920 of file ARMISelLowering.cpp.

3920  {
3921  const ARMBaseRegisterInfo &ARI =
3922  *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
3923  MachineFunction &MF = DAG.getMachineFunction();
3924  MachineFrameInfo *MFI = MF.getFrameInfo();
3925  MFI->setFrameAddressIsTaken(true);
3926 
3927  EVT VT = Op.getValueType();
3928  SDLoc dl(Op); // FIXME probably not meaningful
3929  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3930  unsigned FrameReg = ARI.getFrameRegister(MF);
3931  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3932  while (Depth--)
3933  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3935  false, false, false, 0);
3936  return FrameAddr;
3937 }
void setFrameAddressIsTaken(bool T)
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
unsigned getFrameRegister(const MachineFunction &MF) const override
Abstract Stack Frame Information.
const SDValue & getOperand(unsigned i) const
const TargetRegisterInfo * RegInfo
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
MachineFrameInfo * getFrameInfo()
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
EVT getValueType() const
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue ARMTargetLowering::LowerFSINCOS ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 6088 of file ARMISelLowering.cpp.

6088  {
6090 
6091  // For iOS, we want to call an alternative entry point: __sincos_stret,
6092  // return values are passed via sret.
6093  SDLoc dl(Op);
6094  SDValue Arg = Op.getOperand(0);
6095  EVT ArgVT = Arg.getValueType();
6096  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
6097 
6098  MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6099  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6100 
6101  // Pair of floats / doubles used to pass the result.
6102  StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
6103 
6104  // Create stack object for sret.
6105  const uint64_t ByteSize = TLI.getDataLayout()->getTypeAllocSize(RetTy);
6106  const unsigned StackAlign = TLI.getDataLayout()->getPrefTypeAlignment(RetTy);
6107  int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
6108  SDValue SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
6109 
6110  ArgListTy Args;
6111  ArgListEntry Entry;
6112 
6113  Entry.Node = SRet;
6114  Entry.Ty = RetTy->getPointerTo();
6115  Entry.isSExt = false;
6116  Entry.isZExt = false;
6117  Entry.isSRet = true;
6118  Args.push_back(Entry);
6119 
6120  Entry.Node = Arg;
6121  Entry.Ty = ArgTy;
6122  Entry.isSExt = false;
6123  Entry.isZExt = false;
6124  Args.push_back(Entry);
6125 
6126  const char *LibcallName = (ArgVT == MVT::f64)
6127  ? "__sincos_stret" : "__sincosf_stret";
6128  SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
6129 
6131  CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
6132  .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), Callee,
6133  std::move(Args), 0)
6134  .setDiscardResult();
6135 
6136  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
6137 
6138  SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
6139  MachinePointerInfo(), false, false, false, 0);
6140 
6141  // Address of cos field.
6142  SDValue Add = DAG.getNode(ISD::ADD, dl, getPointerTy(), SRet,
6143  DAG.getIntPtrConstant(ArgVT.getStoreSize()));
6144  SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
6145  MachinePointerInfo(), false, false, false, 0);
6146 
6147  SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
6148  return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
6149  LoadSin.getValue(0), LoadCos.getValue(0));
6150 }
SDValue getValue(unsigned R) const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
unsigned getPrefTypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:693
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
SDValue getExternalSymbol(const char *Sym, EVT VT)
bool isTargetDarwin() const
Definition: ARMSubtarget.h:346
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Abstract Stack Frame Information.
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
unsigned getStoreSize() const
Definition: ValueTypes.h:246
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:221
const DataLayout * getDataLayout() const
std::vector< ArgListEntry > ArgListTy
PointerType * getPointerTo(unsigned AddrSpace=0)
Definition: Type.cpp:753
const char * Args[]
uint64_t getTypeAllocSize(Type *Ty) const
Definition: DataLayout.h:368
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
Definition: Type.cpp:399
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
const ARMSubtarget * Subtarget
MachineFrameInfo * getFrameInfo()
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
EVT getValueType() const
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2535 of file ARMISelLowering.cpp.

2536  {
2538  "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2539  MachineFunction &MF = DAG.getMachineFunction();
2540  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2541  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2542  EVT PtrVT = getPointerTy();
2543  SDLoc dl(Op);
2544  unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2545  ARMConstantPoolValue *CPV =
2546  ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2547  ARMPCLabelIndex, PCAdj);
2548  SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2549  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2550  SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2552  false, false, false, 0);
2553  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2554  return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2555 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
static MachinePointerInfo getConstantPool()
bool isTargetELF() const
Definition: ARMSubtarget.h:354
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual MVT getPointerTy(uint32_t=0) const
bool isThumb() const
Definition: ARMSubtarget.h:400
assert(Globals.size() > 1)
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:450
const ARMSubtarget * Subtarget
static ARMConstantPoolSymbol * Create(LLVMContext &C, const char *s, unsigned ID, unsigned char PCAdj)
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue ARMTargetLowering::LowerGlobalAddressDarwin ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2485 of file ARMISelLowering.cpp.

2486  {
2487  EVT PtrVT = getPointerTy();
2488  SDLoc dl(Op);
2489  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2491 
2492  if (Subtarget->useMovt(DAG.getMachineFunction()))
2493  ++NumMovwMovt;
2494 
2495  // FIXME: Once remat is capable of dealing with instructions with register
2496  // operands, expand this into multiple nodes
2497  unsigned Wrapper =
2499 
2500  SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2501  SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2502 
2503  if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2504  Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2505  MachinePointerInfo::getGOT(), false, false, false, 0);
2506  return Result;
2507 }
Reloc::Model getRelocationModel() const
const TargetMachine & getTargetMachine() const
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
virtual MVT getPointerTy(uint32_t=0) const
#define G(x, y, z)
Definition: MD5.cpp:52
bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const
GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
const ARMSubtarget * Subtarget
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
static MachinePointerInfo getGOT()
bool useMovt(const MachineFunction &MF) const
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue ARMTargetLowering::LowerGlobalAddressELF ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2442 of file ARMISelLowering.cpp.

2443  {
2444  EVT PtrVT = getPointerTy();
2445  SDLoc dl(Op);
2446  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2447  if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2448  bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2449  ARMConstantPoolValue *CPV =
2451  UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2452  SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2453  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2454  SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2455  CPAddr,
2457  false, false, false, 0);
2458  SDValue Chain = Result.getValue(1);
2459  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2460  Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2461  if (!UseGOTOFF)
2462  Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2464  false, false, false, 0);
2465  return Result;
2466  }
2467 
2468  // If we have T2 ops, we can materialize the address directly via movt/movw
2469  // pair. This is always cheaper.
2470  if (Subtarget->useMovt(DAG.getMachineFunction())) {
2471  ++NumMovwMovt;
2472  // FIXME: Once remat is capable of dealing with instructions with register
2473  // operands, expand this into two nodes.
2474  return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2475  DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2476  } else {
2477  SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2478  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2479  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2481  false, false, false, 0);
2482  }
2483 }
SDValue getValue(unsigned R) const
const TargetMachine & getTargetMachine() const
static MachinePointerInfo getConstantPool()
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
virtual MVT getPointerTy(uint32_t=0) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
bool hasHiddenVisibility() const
Definition: GlobalValue.h:122
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:450
const ARMSubtarget * Subtarget
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
static MachinePointerInfo getGOT()
bool useMovt(const MachineFunction &MF) const
bool hasLocalLinkage() const
Definition: GlobalValue.h:261
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Definition: SelectionDAG.h:631
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
SDValue ARMTargetLowering::LowerGlobalAddressWindows ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2509 of file ARMISelLowering.cpp.

2510  {
2511  assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
2513  "Windows on ARM expects to use movw/movt");
2514 
2515  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2516  const ARMII::TOF TargetFlags =
2518  EVT PtrVT = getPointerTy();
2519  SDValue Result;
2520  SDLoc DL(Op);
2521 
2522  ++NumMovwMovt;
2523 
2524  // FIXME: Once remat is capable of dealing with instructions with register
2525  // operands, expand this into two nodes.
2526  Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2527  DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
2528  TargetFlags));
2529  if (GV->hasDLLImportStorageClass())
2530  Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2531  MachinePointerInfo::getGOT(), false, false, false, 0);
2532  return Result;
2533 }
TOF
Target Operand Flag enum.
Definition: ARMBaseInfo.h:278
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
const DataLayout * DL
True if this is a little endian target.
virtual MVT getPointerTy(uint32_t=0) const
assert(Globals.size() > 1)
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:148
const ARMSubtarget * Subtarget
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
static MachinePointerInfo getGOT()
bool useMovt(const MachineFunction &MF) const
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
bool isTargetWindows() const
Definition: ARMSubtarget.h:351
SDValue ARMTargetLowering::LowerGlobalTLSAddress ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 2423 of file ARMISelLowering.cpp.

2423  {
2424  // TODO: implement the "local dynamic" model
2426  "TLS not implemented for non-ELF targets");
2427  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2428 
2429  TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2430 
2431  switch (model) {
2434  return LowerToTLSGeneralDynamicModel(GA, DAG);
2435  case TLSModel::InitialExec:
2436  case TLSModel::LocalExec:
2437  return LowerToTLSExecModels(GA, DAG, model);
2438  }
2439  llvm_unreachable("bogus TLS model");
2440 }
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
const TargetMachine & getTargetMachine() const
bool isTargetELF() const
Definition: ARMSubtarget.h:354
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
assert(Globals.size() > 1)
const ARMSubtarget * Subtarget
SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, SelectionDAG &DAG, TLSModel::Model model) const
TLSModel::Model getTLSModel(const GlobalValue *GV) const
SDValue ARMTargetLowering::LowerINTRINSIC_WO_CHAIN ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
) const
private

Definition at line 2574 of file ARMISelLowering.cpp.

2575  {
2576  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2577  SDLoc dl(Op);
2578  switch (IntNo) {
2579  default: return SDValue(); // Don't custom lower most intrinsics.
2580  case Intrinsic::arm_rbit: {
2581  assert(Op.getOperand(1).getValueType() == MVT::i32 &&
2582  "RBIT intrinsic must have i32 type!");
2583  return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1));
2584  }
2585  case Intrinsic::arm_thread_pointer: {
2586  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2587  return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2588  }
2589  case Intrinsic::eh_sjlj_lsda: {
2590  MachineFunction &MF = DAG.getMachineFunction();
2592  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2593  EVT PtrVT = getPointerTy();
2595  SDValue CPAddr;
2596  unsigned PCAdj = (RelocM != Reloc::PIC_)
2597  ? 0 : (Subtarget->isThumb() ? 4 : 8);
2598  ARMConstantPoolValue *CPV =
2600  ARMCP::CPLSDA, PCAdj);
2601  CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2602  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2603  SDValue Result =
2604  DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2606  false, false, false, 0);
2607 
2608  if (RelocM == Reloc::PIC_) {
2609  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2610  Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2611  }
2612  return Result;
2613  }
2614  case Intrinsic::arm_neon_vmulls:
2615  case Intrinsic::arm_neon_vmullu: {
2616  unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2618  return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2619  Op.getOperand(1), Op.getOperand(2));
2620  }
2621  }
2622 }
Reloc::Model getRelocationModel() const
const TargetMachine & getTargetMachine() const
const Function * getFunction() const
static MachinePointerInfo getConstantPool()
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual MVT getPointerTy(uint32_t=0) const
bool isThumb() const
Definition: ARMSubtarget.h:400
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:450
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
SDValue ARMTargetLowering::LowerMemOpCallTo ( SDValue  Chain,
SDValue  StackPtr,
SDValue  Arg,
SDLoc  dl,
SelectionDAG DAG,
const CCValAssign VA,
ISD::ArgFlagsTy  Flags 
) const
private

LowerMemOpCallTo - Store the argument to the stack.

Definition at line 1347 of file ARMISelLowering.cpp.

1351  {
1352  unsigned LocMemOffset = VA.getLocMemOffset();
1353  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1354  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1355  return DAG.getStore(Chain, dl, Arg, PtrOff,
1356  MachinePointerInfo::getStack(LocMemOffset),
1357  false, false, 0);
1358 }
virtual MVT getPointerTy(uint32_t=0) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
static MachinePointerInfo getStack(int64_t Offset)
getStack - stack pointer relative access.
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getLocMemOffset() const
SDValue ARMTargetLowering::LowerOperation ( SDValue  Op,
SelectionDAG DAG 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 6199 of file ARMISelLowering.cpp.

6199  {
6200  switch (Op.getOpcode()) {
6201  default: llvm_unreachable("Don't know how to custom lower this!");
6202  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6203  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6204  case ISD::GlobalAddress:
6205  switch (Subtarget->getTargetTriple().getObjectFormat()) {
6206  default: llvm_unreachable("unknown object format");
6207  case Triple::COFF:
6208  return LowerGlobalAddressWindows(Op, DAG);
6209  case Triple::ELF:
6210  return LowerGlobalAddressELF(Op, DAG);
6211  case Triple::MachO:
6212  return LowerGlobalAddressDarwin(Op, DAG);
6213  }
6214  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6215  case ISD::SELECT: return LowerSELECT(Op, DAG);
6216  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6217  case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6218  case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6219  case ISD::VASTART: return LowerVASTART(Op, DAG);
6220  case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6221  case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6222  case ISD::SINT_TO_FP:
6223  case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6224  case ISD::FP_TO_SINT:
6225  case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6226  case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6227  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6228  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6229  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6230  case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6231  case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6232  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6233  Subtarget);
6234  case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6235  case ISD::SHL:
6236  case ISD::SRL:
6237  case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6238  case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6239  case ISD::SRL_PARTS:
6240  case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6241  case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6242  case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6243  case ISD::SETCC: return LowerVSETCC(Op, DAG);
6244  case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6245  case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6246  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6247  case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6248  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6249  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6250  case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6251  case ISD::MUL: return LowerMUL(Op, DAG);
6252  case ISD::SDIV: return LowerSDIV(Op, DAG);
6253  case ISD::UDIV: return LowerUDIV(Op, DAG);
6254  case ISD::ADDC:
6255  case ISD::ADDE:
6256  case ISD::SUBC:
6257  case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6258  case ISD::SADDO:
6259  case ISD::UADDO:
6260  case ISD::SSUBO:
6261  case ISD::USUBO:
6262  return LowerXALUO(Op, DAG);
6263  case ISD::ATOMIC_LOAD:
6264  case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6265  case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6266  case ISD::SDIVREM:
6267  case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6270  return LowerDYNAMIC_STACKALLOC(Op, DAG);
6271  llvm_unreachable("Don't know how to custom lower this!");
6272  }
6273 }
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG)
static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG)
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const
SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const
SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG)
static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const
Same for subtraction.
Definition: ISDOpcodes.h:221
The address of the GOT.
Definition: ISDOpcodes.h:66
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG)
static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG)
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
ObjectFormatType getObjectFormat() const
getFormat - Get the object format for this triple.
Definition: Triple.h:234
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const
static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG)
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:344
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
const ARMSubtarget * Subtarget
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG)
SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const
SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:490
static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG)
static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
bool isWindowsItaniumEnvironment() const
Test whether the architecture is 64-bit.
Definition: Triple.h:378
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG)
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG)
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
void TargetLowering::LowerOperationWrapper ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
) const
virtualinherited

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. It replaces the LowerOperation callback in the type Legalizer. The reason we can not do away with LowerOperation entirely is that LegalizeDAG isn't yet ready to use this callback.

TODO: Consider merging with ReplaceNodeResults.

The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all. The default implementation calls LowerOperation.

Reimplemented in llvm::MipsTargetLowering.

Definition at line 7332 of file SelectionDAGBuilder.cpp.

7334  {
7335  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7336  if (Res.getNode())
7337  Results.push_back(Res);
7338 }
SDNode * getNode() const
get the SDNode which holds the desired result
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
SDValue ARMTargetLowering::LowerReturn ( SDValue  Chain,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
const SmallVectorImpl< SDValue > &  OutVals,
SDLoc  dl,
SelectionDAG DAG 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2090 of file ARMISelLowering.cpp.

2094  {
2095 
2096  // CCValAssign - represent the assignment of the return value to a location.
2098 
2099  // CCState - Info about the registers and stack slots.
2100  ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2101  getTargetMachine(), RVLocs, *DAG.getContext(), Call);
2102 
2103  // Analyze outgoing return values.
2104  CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2105  isVarArg));
2106 
2107  SDValue Flag;
2108  SmallVector<SDValue, 4> RetOps;
2109  RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2110  bool isLittleEndian = Subtarget->isLittle();
2111 
2112  // Copy the result values into the output registers.
2113  for (unsigned i = 0, realRVLocIdx = 0;
2114  i != RVLocs.size();
2115  ++i, ++realRVLocIdx) {
2116  CCValAssign &VA = RVLocs[i];
2117  assert(VA.isRegLoc() && "Can only return in registers!");
2118 
2119  SDValue Arg = OutVals[realRVLocIdx];
2120 
2121  switch (VA.getLocInfo()) {
2122  default: llvm_unreachable("Unknown loc info!");
2123  case CCValAssign::Full: break;
2124  case CCValAssign::BCvt:
2125  Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2126  break;
2127  }
2128 
2129  if (VA.needsCustom()) {
2130  if (VA.getLocVT() == MVT::v2f64) {
2131  // Extract the first half and return it in two registers.
2132  SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2133  DAG.getConstant(0, MVT::i32));
2134  SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2135  DAG.getVTList(MVT::i32, MVT::i32), Half);
2136 
2137  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2138  HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2139  Flag);
2140  Flag = Chain.getValue(1);
2141  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2142  VA = RVLocs[++i]; // skip ahead to next loc
2143  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2144  HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2145  Flag);
2146  Flag = Chain.getValue(1);
2147  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2148  VA = RVLocs[++i]; // skip ahead to next loc
2149 
2150  // Extract the 2nd half and fall through to handle it as an f64 value.
2151  Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2152  DAG.getConstant(1, MVT::i32));
2153  }
2154  // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2155  // available.
2156  SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2157  DAG.getVTList(MVT::i32, MVT::i32), Arg);
2158  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2159  fmrrd.getValue(isLittleEndian ? 0 : 1),
2160  Flag);
2161  Flag = Chain.getValue(1);
2162  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2163  VA = RVLocs[++i]; // skip ahead to next loc
2164  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2165  fmrrd.getValue(isLittleEndian ? 1 : 0),
2166  Flag);
2167  } else
2168  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2169 
2170  // Guarantee that all emitted copies are
2171  // stuck together, avoiding something bad.
2172  Flag = Chain.getValue(1);
2173  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2174  }
2175 
2176  // Update chain and glue.
2177  RetOps[0] = Chain;
2178  if (Flag.getNode())
2179  RetOps.push_back(Flag);
2180 
2181  // CPUs which aren't M-class use a special sequence to return from
2182  // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2183  // though we use "subs pc, lr, #N").
2184  //
2185  // M-class CPUs actually use a normal return sequence with a special
2186  // (hardware-provided) value in LR, so the normal code path works.
2187  if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2188  !Subtarget->isMClass()) {
2189  if (Subtarget->isThumb1Only())
2190  report_fatal_error("interrupt attribute is not supported in Thumb1");
2191  return LowerInterruptReturn(RetOps, dl, DAG);
2192  }
2193 
2194  return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2195 }
SDValue getValue(unsigned R) const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
LocInfo getLocInfo() const
const TargetMachine & getTargetMachine() const
const Function * getFunction() const
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
bool isRegLoc() const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
static SDValue LowerInterruptReturn(SmallVectorImpl< SDValue > &RetOps, SDLoc DL, SelectionDAG &DAG)
bool isLittleEndian() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
bool isLittle() const
Definition: ARMSubtarget.h:420
SDVTList getVTList(EVT VT)
unsigned getLocReg() const
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
MVT getLocVT() const
bool isMClass() const
Definition: ARMSubtarget.h:404
bool needsCustom() const
CCValAssign - Represent assignment of one arg/retval to a location.
const ARMSubtarget * Subtarget
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:200
CCAssignFn * CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getRegister(unsigned Reg, EVT VT)
SDValue ARMTargetLowering::LowerRETURNADDR ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3896 of file ARMISelLowering.cpp.

3896  {
3897  MachineFunction &MF = DAG.getMachineFunction();
3898  MachineFrameInfo *MFI = MF.getFrameInfo();
3899  MFI->setReturnAddressIsTaken(true);
3900 
3902  return SDValue();
3903 
3904  EVT VT = Op.getValueType();
3905  SDLoc dl(Op);
3906  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3907  if (Depth) {
3908  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3909  SDValue Offset = DAG.getConstant(4, MVT::i32);
3910  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3911  DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3912  MachinePointerInfo(), false, false, false, 0);
3913  }
3914 
3915  // Return LR, which contains the return address. Mark it an implicit live-in.
3916  unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3917  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3918 }
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Reg
All possible values of the reg field in the ModR/M byte.
Abstract Stack Frame Information.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
const SDValue & getOperand(unsigned i) const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
MachineFrameInfo * getFrameInfo()
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
const TargetRegisterClass * getRegClassFor(MVT VT) const override
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
void setReturnAddressIsTaken(bool s)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue ARMTargetLowering::LowerSELECT ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3308 of file ARMISelLowering.cpp.

3308  {
3309  SDValue Cond = Op.getOperand(0);
3310  SDValue SelectTrue = Op.getOperand(1);
3311  SDValue SelectFalse = Op.getOperand(2);
3312  SDLoc dl(Op);
3313  unsigned Opc = Cond.getOpcode();
3314 
3315  if (Cond.getResNo() == 1 &&
3316  (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3317  Opc == ISD::USUBO)) {
3318  if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
3319  return SDValue();
3320 
3321  SDValue Value, OverflowCmp;
3322  SDValue ARMcc;
3323  std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
3324  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3325  EVT VT = Op.getValueType();
3326 
3327  return DAG.getNode(ARMISD::CMOV, SDLoc(Op), VT, SelectTrue, SelectFalse,
3328  ARMcc, CCR, OverflowCmp);
3329 
3330  }
3331 
3332  // Convert:
3333  //
3334  // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3335  // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3336  //
3337  if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3338  const ConstantSDNode *CMOVTrue =
3340  const ConstantSDNode *CMOVFalse =
3342 
3343  if (CMOVTrue && CMOVFalse) {
3344  unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3345  unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3346 
3347  SDValue True;
3348  SDValue False;
3349  if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3350  True = SelectTrue;
3351  False = SelectFalse;
3352  } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3353  True = SelectFalse;
3354  False = SelectTrue;
3355  }
3356 
3357  if (True.getNode() && False.getNode()) {
3358  EVT VT = Op.getValueType();
3359  SDValue ARMcc = Cond.getOperand(2);
3360  SDValue CCR = Cond.getOperand(3);
3361  SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3362  assert(True.getValueType() == VT);
3363  return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
3364  }
3365  }
3366  }
3367 
3368  // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3369  // undefined bits before doing a full-word comparison with zero.
3370  Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3371  DAG.getConstant(1, Cond.getValueType()));
3372 
3373  return DAG.getSelectCC(dl, Cond,
3374  DAG.getConstant(0, Cond.getValueType()),
3375  SelectTrue, SelectFalse, ISD::SETNE);
3376 }
bool hasOneUse() const
SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Definition: SelectionDAG.h:716
Same for subtraction.
Definition: ISDOpcodes.h:221
unsigned getResNo() const
get the index which selects a specific result in the SDNode
EVT getValueType(unsigned ResNo) const
static int Value(bit_value_t V)
SDNode * getNode() const
get the SDNode which holds the desired result
std::pair< SDValue, SDValue > getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getRegister(unsigned Reg, EVT VT)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
uint64_t getZExtValue() const
SDValue ARMTargetLowering::LowerSELECT_CC ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3433 of file ARMISelLowering.cpp.

3433  {
3434  EVT VT = Op.getValueType();
3435  SDValue LHS = Op.getOperand(0);
3436  SDValue RHS = Op.getOperand(1);
3437  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3438  SDValue TrueVal = Op.getOperand(2);
3439  SDValue FalseVal = Op.getOperand(3);
3440  SDLoc dl(Op);
3441 
3442  if (LHS.getValueType() == MVT::i32) {
3443  // Try to generate VSEL on ARMv8.
3444  // The VSEL instruction can't use all the usual ARM condition
3445  // codes: it only has two bits to select the condition code, so it's
3446  // constrained to use only GE, GT, VS and EQ.
3447  //
3448  // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3449  // swap the operands of the previous compare instruction (effectively
3450  // inverting the compare condition, swapping 'less' and 'greater') and
3451  // sometimes need to swap the operands to the VSEL (which inverts the
3452  // condition in the sense of firing whenever the previous condition didn't)
3453  if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3454  TrueVal.getValueType() == MVT::f64)) {
3456  if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3457  CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3458  CC = getInverseCCForVSEL(CC);
3459  std::swap(TrueVal, FalseVal);
3460  }
3461  }
3462 
3463  SDValue ARMcc;
3464  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3465  SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3466  return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3467  Cmp);
3468  }
3469 
3470  ARMCC::CondCodes CondCode, CondCode2;
3471  FPCCToARMCC(CC, CondCode, CondCode2);
3472 
3473  // Try to generate VSEL on ARMv8.
3474  if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3475  TrueVal.getValueType() == MVT::f64)) {
3476  // We can select VMAXNM/VMINNM from a compare followed by a select with the
3477  // same operands, as follows:
3478  // c = fcmp [ogt, olt, ugt, ult] a, b
3479  // select c, a, b
3480  // We only do this in unsafe-fp-math, because signed zeros and NaNs are
3481  // handled differently than the original code sequence.
3482  if (getTargetMachine().Options.UnsafeFPMath && LHS == TrueVal &&
3483  RHS == FalseVal) {
3484  if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3485  return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3486  if (CC == ISD::SETOLT || CC == ISD::SETULT)
3487  return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3488  }
3489 
3490  bool swpCmpOps = false;
3491  bool swpVselOps = false;
3492  checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3493 
3494  if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3495  CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3496  if (swpCmpOps)
3497  std::swap(LHS, RHS);
3498  if (swpVselOps)
3499  std::swap(TrueVal, FalseVal);
3500  }
3501  }
3502 
3503  SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3504  SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3505  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3506  SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
3507  ARMcc, CCR, Cmp);
3508  if (CondCode2 != ARMCC::AL) {
3509  SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
3510  // FIXME: Needs another CMP because flag can have but one use.
3511  SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3512  Result = DAG.getNode(ARMISD::CMOV, dl, VT,
3513  Result, TrueVal, ARMcc2, CCR, Cmp2);
3514  }
3515  return Result;
3516 }
const TargetMachine & getTargetMachine() const
SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl) const
Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
bool hasFPARMv8() const
Definition: ARMSubtarget.h:310
const SDValue & getOperand(unsigned i) const
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const
static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC)
IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.
const ARMSubtarget * getSubtarget() const
static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps)
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2)
FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getRegister(unsigned Reg, EVT VT)
SDValue ARMTargetLowering::LowerShiftLeftParts ( SDValue  Op,
SelectionDAG DAG 
) const
private

LowerShiftLeftParts - Lower SHL_PARTS, which returns two i32 values and take a 2 x i32 value to shift plus a shift amount.

Definition at line 4049 of file ARMISelLowering.cpp.

4050  {
4051  assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4052  EVT VT = Op.getValueType();
4053  unsigned VTBits = VT.getSizeInBits();
4054  SDLoc dl(Op);
4055  SDValue ShOpLo = Op.getOperand(0);
4056  SDValue ShOpHi = Op.getOperand(1);
4057  SDValue ShAmt = Op.getOperand(2);
4058  SDValue ARMcc;
4059 
4060  assert(Op.getOpcode() == ISD::SHL_PARTS);
4061  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4062  DAG.getConstant(VTBits, MVT::i32), ShAmt);
4063  SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4064  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4065  DAG.getConstant(VTBits, MVT::i32));
4066  SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4067  SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4068 
4069  SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4070  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4071  SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
4072  ARMcc, DAG, dl);
4073  SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4074  SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
4075  CCR, Cmp);
4076 
4077  SDValue Ops[2] = { Lo, Hi };
4078  return DAG.getMergeValues(Ops, dl);
4079 }
unsigned getNumOperands() const
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const
unsigned getOpcode() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getRegister(unsigned Reg, EVT VT)
SDValue ARMTargetLowering::LowerShiftRightParts ( SDValue  Op,
SelectionDAG DAG 
) const
private

LowerShiftRightParts - Lower SRA_PARTS, which returns two i32 values and take a 2 x i32 value to shift plus a shift amount.

Definition at line 4013 of file ARMISelLowering.cpp.

4014  {
4015  assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4016  EVT VT = Op.getValueType();
4017  unsigned VTBits = VT.getSizeInBits();
4018  SDLoc dl(Op);
4019  SDValue ShOpLo = Op.getOperand(0);
4020  SDValue ShOpHi = Op.getOperand(1);
4021  SDValue ShAmt = Op.getOperand(2);
4022  SDValue ARMcc;
4023  unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4024 
4026 
4027  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4028  DAG.getConstant(VTBits, MVT::i32), ShAmt);
4029  SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4030  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4031  DAG.getConstant(VTBits, MVT::i32));
4032  SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4033  SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4034  SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4035 
4036  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4037  SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
4038  ARMcc, DAG, dl);
4039  SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4040  SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
4041  CCR, Cmp);
4042 
4043  SDValue Ops[2] = { Lo, Hi };
4044  return DAG.getMergeValues(Ops, dl);
4045 }
unsigned getNumOperands() const
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const
unsigned getOpcode() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getRegister(unsigned Reg, EVT VT)
SDValue ARMTargetLowering::LowerToTLSExecModels ( GlobalAddressSDNode GA,
SelectionDAG DAG,
TLSModel::Model  model 
) const
private

Definition at line 2371 of file ARMISelLowering.cpp.

2373  {
2374  const GlobalValue *GV = GA->getGlobal();
2375  SDLoc dl(GA);
2376  SDValue Offset;
2377  SDValue Chain = DAG.getEntryNode();
2378  EVT PtrVT = getPointerTy();
2379  // Get the Thread Pointer
2381 
2382  if (model == TLSModel::InitialExec) {
2383  MachineFunction &MF = DAG.getMachineFunction();
2385  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2386  // Initial exec model.
2387  unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2388  ARMConstantPoolValue *CPV =
2391  true);
2392  Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2393  Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2394  Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2396  false, false, false, 0);
2397  Chain = Offset.getValue(1);
2398 
2399  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2400  Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2401 
2402  Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2404  false, false, false, 0);
2405  } else {
2406  // local exec model
2407  assert(model == TLSModel::LocalExec);
2408  ARMConstantPoolValue *CPV =
2410  Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2411  Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2412  Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2414  false, false, false, 0);
2415  }
2416 
2417  // The address of the thread local variable is the add of the thread
2418  // pointer with the offset of the variable.
2419  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2420 }
SDValue getValue(unsigned R) const
const GlobalValue * getGlobal() const
static MachinePointerInfo getConstantPool()
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual MVT getPointerTy(uint32_t=0) const
bool isThumb() const
Definition: ARMSubtarget.h:400
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
assert(Globals.size() > 1)
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:450
const ARMSubtarget * Subtarget
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
SDValue ARMTargetLowering::LowerToTLSGeneralDynamicModel ( GlobalAddressSDNode GA,
SelectionDAG DAG 
) const
private

Definition at line 2329 of file ARMISelLowering.cpp.

2330  {
2331  SDLoc dl(GA);
2332  EVT PtrVT = getPointerTy();
2333  unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2334  MachineFunction &MF = DAG.getMachineFunction();
2336  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2337  ARMConstantPoolValue *CPV =
2339  ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2340  SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2341  Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2342  Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2344  false, false, false, 0);
2345  SDValue Chain = Argument.getValue(1);
2346 
2347  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2348  Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2349 
2350  // call __tls_get_addr.
2351  ArgListTy Args;
2352  ArgListEntry Entry;
2353  Entry.Node = Argument;
2354  Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2355  Args.push_back(Entry);
2356 
2357  // FIXME: is there useful debug info available here?
2359  CLI.setDebugLoc(dl).setChain(Chain)
2360  .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2361  DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args),
2362  0);
2363 
2364  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2365  return CallResult.first;
2366 }
SDValue getValue(unsigned R) const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
LLVM Argument representation.
Definition: Argument.h:35
const GlobalValue * getGlobal() const
static MachinePointerInfo getConstantPool()
SDValue getExternalSymbol(const char *Sym, EVT VT)
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual MVT getPointerTy(uint32_t=0) const
bool isThumb() const
Definition: ARMSubtarget.h:400
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
std::vector< ArgListEntry > ArgListTy
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:450
const char * Args[]
const ARMSubtarget * Subtarget
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:235
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
SDValue ARMTargetLowering::LowerXALUO ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 3286 of file ARMISelLowering.cpp.

3286  {
3287  // Let legalize expand this if it isn't a legal type yet.
3289  return SDValue();
3290 
3291  SDValue Value, OverflowCmp;
3292  SDValue ARMcc;
3293  std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3294  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3295  // We use 0 and 1 as false and true values.
3296  SDValue TVal = DAG.getConstant(1, MVT::i32);
3297  SDValue FVal = DAG.getConstant(0, MVT::i32);
3298  EVT VT = Op.getValueType();
3299 
3300  SDValue Overflow = DAG.getNode(ARMISD::CMOV, SDLoc(Op), VT, TVal, FVal,
3301  ARMcc, CCR, OverflowCmp);
3302 
3303  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3304  return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
3305 }
SDVTList getVTList(EVT VT)
static int Value(bit_value_t V)
std::pair< SDValue, SDValue > getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const
bool isTypeLegal(EVT VT) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getRegister(unsigned Reg, EVT VT)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
const char * TargetLowering::LowerXConstraint ( EVT  ConstraintVT) const
virtualinherited

Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. This returns null if there is no replacement to make.

LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2091 of file TargetLowering.cpp.

2091  {
2092  if (ConstraintVT.isInteger())
2093  return "r";
2094  if (ConstraintVT.isFloatingPoint())
2095  return "f"; // works for many targets
2096  return nullptr;
2097 }
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
std::pair< SDValue, SDValue > TargetLowering::makeLibCall ( SelectionDAG DAG,
RTLIB::Libcall  LC,
EVT  RetVT,
const SDValue Ops,
unsigned  NumOps,
bool  isSigned,
SDLoc  dl,
bool  doesNotReturn = false,
bool  isReturnValueUsed = true 
) const
inherited

Returns a pair of (return value, chain).

Generate a libcall taking the given operands as arguments and returning a result of type RetVT.

Definition at line 86 of file TargetLowering.cpp.

91  {
93  Args.reserve(NumOps);
94 
96  for (unsigned i = 0; i != NumOps; ++i) {
97  Entry.Node = Ops[i];
98  Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99  Entry.isSExt = isSigned;
100  Entry.isZExt = !isSigned;
101  Args.push_back(Entry);
102  }
104 
105  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
107  CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
108  .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
109  .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
110  .setSExtResult(isSigned).setZExtResult(!isSigned);
111  return LowerCallTo(CLI);
112 }
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
SDValue getExternalSymbol(const char *Sym, EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
std::vector< ArgListEntry > ArgListTy
const char * Args[]
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
EVT getValueType() const
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
bool ARMTargetLowering::mayBeEmittedAsTailCall ( CallInst CI) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2262 of file ARMISelLowering.cpp.

2262  {
2263  if (!Subtarget->supportsTailCall())
2264  return false;
2265 
2267  return false;
2268 
2269  return !Subtarget->isThumb1Only();
2270 }
const TargetMachine & getTargetMachine() const
bool isThumb1Only() const
Definition: ARMSubtarget.h:401
bool supportsTailCall() const
Definition: ARMSubtarget.h:412
const ARMSubtarget * Subtarget
bool isTailCall() const
SDValue ARMTargetLowering::OptimizeVFPBrcond ( SDValue  Op,
SelectionDAG DAG 
) const
private

OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some f32 and even f64 comparisons to integer ones.

Definition at line 3588 of file ARMISelLowering.cpp.

3588  {
3589  SDValue Chain = Op.getOperand(0);
3590  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3591  SDValue LHS = Op.getOperand(2);
3592  SDValue RHS = Op.getOperand(3);
3593  SDValue Dest = Op.getOperand(4);
3594  SDLoc dl(Op);
3595 
3596  bool LHSSeenZero = false;
3597  bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3598  bool RHSSeenZero = false;
3599  bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3600  if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3601  // If unsafe fp math optimization is enabled and there are no other uses of
3602  // the CMP operands, and the condition code is EQ or NE, we can optimize it
3603  // to an integer comparison.
3604  if (CC == ISD::SETOEQ)
3605  CC = ISD::SETEQ;
3606  else if (CC == ISD::SETUNE)
3607  CC = ISD::SETNE;
3608 
3609  SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3610  SDValue ARMcc;
3611  if (LHS.getValueType() == MVT::f32) {
3612  LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3613  bitcastf32Toi32(LHS, DAG), Mask);
3614  RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3615  bitcastf32Toi32(RHS, DAG), Mask);
3616  SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3617  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3618  return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3619  Chain, Dest, ARMcc, CCR, Cmp);
3620  }
3621 
3622  SDValue LHS1, LHS2;
3623  SDValue RHS1, RHS2;
3624  expandf64Toi32(LHS, DAG, LHS1, LHS2);
3625  expandf64Toi32(RHS, DAG, RHS1, RHS2);
3626  LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3627  RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3629  ARMcc = DAG.getConstant(CondCode, MVT::i32);
3630  SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3631  SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3632  return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
3633  }
3634 
3635  return SDValue();
3636 }
SDVTList getVTList(EVT VT)
const SDValue & getOperand(unsigned i) const
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const
static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC)
IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.
static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2)
const ARMSubtarget * Subtarget
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
static bool canChangeToInt(SDValue Op, bool &SeenZero, const ARMSubtarget *Subtarget)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getRegister(unsigned Reg, EVT VT)
static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG)
TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints ( ImmutableCallSite  CS) const
virtualinherited

Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

ParseConstraints - Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

ConstraintOperands - Information about all of the constraints.

Definition at line 2233 of file TargetLowering.cpp.

2234  {
2235  /// ConstraintOperands - Information about all of the constraints.
2236  AsmOperandInfoVector ConstraintOperands;
2237  const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2238  unsigned maCount = 0; // Largest number of multiple alternative constraints.
2239 
2240  // Do a prepass over the constraints, canonicalizing them, and building up the
2241  // ConstraintOperands list.
2243  ConstraintInfos = IA->ParseConstraints();
2244 
2245  unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2246  unsigned ResNo = 0; // ResNo - The result number of the next output.
2247 
2248  for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2249  ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2250  AsmOperandInfo &OpInfo = ConstraintOperands.back();
2251 
2252  // Update multiple alternative constraint count.
2253  if (OpInfo.multipleAlternatives.size() > maCount)
2254  maCount = OpInfo.multipleAlternatives.size();
2255 
2256  OpInfo.ConstraintVT = MVT::Other;
2257 
2258  // Compute the value type for each operand.
2259  switch (OpInfo.Type) {
2260  case InlineAsm::isOutput:
2261  // Indirect outputs just consume an argument.
2262  if (OpInfo.isIndirect) {
2263  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2264  break;
2265  }
2266 
2267  // The return value of the call is this value. As such, there is no
2268  // corresponding argument.
2269  assert(!CS.getType()->isVoidTy() &&
2270  "Bad inline asm!");
2271  if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2272  OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2273  } else {
2274  assert(ResNo == 0 && "Asm only has one result!");
2275  OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2276  }
2277  ++ResNo;
2278  break;
2279  case InlineAsm::isInput:
2280  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2281  break;
2282  case InlineAsm::isClobber:
2283  // Nothing to do.
2284  break;
2285  }
2286 
2287  if (OpInfo.CallOperandVal) {
2288  llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2289  if (OpInfo.isIndirect) {
2290  llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2291  if (!PtrTy)
2292  report_fatal_error("Indirect operand for inline asm not a pointer!");
2293  OpTy = PtrTy->getElementType();
2294  }
2295 
2296  // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2297  if (StructType *STy = dyn_cast<StructType>(OpTy))
2298  if (STy->getNumElements() == 1)
2299  OpTy = STy->getElementType(0);
2300 
2301  // If OpTy is not a single value, it may be a struct/union that we
2302  // can tile with integers.
2303  if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2304  unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2305  switch (BitSize) {
2306  default: break;
2307  case 1:
2308  case 8:
2309  case 16:
2310  case 32:
2311  case 64:
2312  case 128:
2313  OpInfo.ConstraintVT =
2314  MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2315  break;
2316  }
2317  } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2318  unsigned PtrSize
2319  = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2320  OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2321  } else {
2322  OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2323  }
2324  }
2325  }
2326 
2327  // If we have multiple alternative constraints, select the best alternative.
2328  if (ConstraintInfos.size()) {
2329  if (maCount) {
2330  unsigned bestMAIndex = 0;
2331  int bestWeight = -1;
2332  // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2333  int weight = -1;
2334  unsigned maIndex;
2335  // Compute the sums of the weights for each alternative, keeping track
2336  // of the best (highest weight) one so far.
2337  for (maIndex = 0; maIndex < maCount; ++maIndex) {
2338  int weightSum = 0;
2339  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2340  cIndex != eIndex; ++cIndex) {
2341  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2342  if (OpInfo.Type == InlineAsm::isClobber)
2343  continue;
2344 
2345  // If this is an output operand with a matching input operand,
2346  // look up the matching input. If their types mismatch, e.g. one
2347  // is an integer, the other is floating point, or their sizes are
2348  // different, flag it as an maCantMatch.
2349  if (OpInfo.hasMatchingInput()) {
2350  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2351  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2352  if ((OpInfo.ConstraintVT.isInteger() !=
2353  Input.ConstraintVT.isInteger()) ||
2354  (OpInfo.ConstraintVT.getSizeInBits() !=
2355  Input.ConstraintVT.getSizeInBits())) {
2356  weightSum = -1; // Can't match.
2357  break;
2358  }
2359  }
2360  }
2361  weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2362  if (weight == -1) {
2363  weightSum = -1;
2364  break;
2365  }
2366  weightSum += weight;
2367  }
2368  // Update best.
2369  if (weightSum > bestWeight) {
2370  bestWeight = weightSum;
2371  bestMAIndex = maIndex;
2372  }
2373  }
2374 
2375  // Now select chosen alternative in each constraint.
2376  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2377  cIndex != eIndex; ++cIndex) {
2378  AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2379  if (cInfo.Type == InlineAsm::isClobber)
2380  continue;
2381  cInfo.selectAlternative(bestMAIndex);
2382  }
2383  }
2384  }
2385 
2386  // Check and hook up tied operands, choose constraint code to use.
2387  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2388  cIndex != eIndex; ++cIndex) {
2389  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2390 
2391  // If this is an output operand with a matching input operand, look up the
2392  // matching input. If their types mismatch, e.g. one is an integer, the
2393  // other is floating point, or their sizes are different, flag it as an
2394  // error.
2395  if (OpInfo.hasMatchingInput()) {
2396  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2397 
2398  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2399  std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2400  getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
2401  OpInfo.ConstraintVT);
2402  std::pair<unsigned, const TargetRegisterClass*> InputRC =
2403  getRegForInlineAsmConstraint(Input.ConstraintCode,
2404  Input.ConstraintVT);
2405  if ((OpInfo.ConstraintVT.isInteger() !=
2406  Input.ConstraintVT.isInteger()) ||
2407  (MatchRC.second != InputRC.second)) {
2408  report_fatal_error("Unsupported asm: input constraint"
2409  " with a matching output constraint of"
2410  " incompatible type!");
2411  }
2412  }
2413 
2414  }
2415  }
2416 
2417  return ConstraintOperands;
2418 }
static MVT getIntegerVT(unsigned BitWidth)
Type * getType() const
Definition: CallSite.h:157
ValTy * getArgument(unsigned ArgNo) const
Definition: CallSite.h:113
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
bool isSingleValueType() const
Definition: Type.h:250
MVT getSimpleValueType(Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
ValTy * getCalledValue() const
Definition: CallSite.h:85
Type * getElementType() const
Definition: DerivedTypes.h:319
assert(Globals.size() > 1)
const DataLayout * getDataLayout() const
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:247
std::vector< AsmOperandInfo > AsmOperandInfoVector
static IntegerType * get(LLVMContext &C, unsigned NumBits)
Get or create an IntegerType instance.
Definition: Type.cpp:299
static cl::opt< std::string > Input(cl::Positional, cl::desc("<input>"), cl::init("-"))
bool isSized(SmallPtrSet< const Type *, 4 > *Visited=nullptr) const
Definition: Type.h:268
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
unsigned getPointerSizeInBits(unsigned AS=0) const
Definition: DataLayout.h:313
LLVM Value Representation.
Definition: Value.h:69
virtual ConstraintWeight getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const
uint64_t getTypeSizeInBits(Type *Ty) const
Definition: DataLayout.h:522
std::vector< ConstraintInfo > ConstraintInfoVector
Definition: InlineAsm.h:118
static ConstraintInfoVector ParseConstraints(StringRef ConstraintString)
Definition: InlineAsm.cpp:203
bool isVoidTy() const
isVoidTy - Return true if this is 'void'.
Definition: Type.h:137
void ARMTargetLowering::PassF64ArgInRegs ( SDLoc  dl,
SelectionDAG DAG,
SDValue  Chain,
SDValue Arg,
RegsToPassVector RegsToPass,
CCValAssign VA,
CCValAssign NextVA,
SDValue StackPtr,
SmallVectorImpl< SDValue > &  MemOpChains,
ISD::ArgFlagsTy  Flags 
) const
private

Definition at line 1360 of file ARMISelLowering.cpp.

1366  {
1367 
1368  SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1369  DAG.getVTList(MVT::i32, MVT::i32), Arg);
1370  unsigned id = Subtarget->isLittle() ? 0 : 1;
1371  RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1372 
1373  if (NextVA.isRegLoc())
1374  RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1375  else {
1376  assert(NextVA.isMemLoc());
1377  if (!StackPtr.getNode())
1378  StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1379 
1380  MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1381  dl, DAG, NextVA,
1382  Flags));
1383  }
1384 }
SDValue getValue(unsigned R) const
bool isRegLoc() const
bool isLittle() const
Definition: ARMSubtarget.h:420
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
LowerMemOpCallTo - Store the argument to the stack.
unsigned getLocReg() const
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
const ARMSubtarget * Subtarget
bool isMemLoc() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue ARMTargetLowering::PerformCMOVCombine ( SDNode N,
SelectionDAG DAG 
) const

PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.

FIXME: Turn this into a target neutral optimization?

Definition at line 9570 of file ARMISelLowering.cpp.

9570  {
9571  SDValue Cmp = N->getOperand(4);
9572  if (Cmp.getOpcode() != ARMISD::CMPZ)
9573  // Only looking at EQ and NE cases.
9574  return SDValue();
9575 
9576  EVT VT = N->getValueType(0);
9577  SDLoc dl(N);
9578  SDValue LHS = Cmp.getOperand(0);
9579  SDValue RHS = Cmp.getOperand(1);
9580  SDValue FalseVal = N->getOperand(0);
9581  SDValue TrueVal = N->getOperand(1);
9582  SDValue ARMcc = N->getOperand(2);
9583  ARMCC::CondCodes CC =
9584  (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
9585 
9586  // Simplify
9587  // mov r1, r0
9588  // cmp r1, x
9589  // mov r0, y
9590  // moveq r0, x
9591  // to
9592  // cmp r0, x
9593  // movne r0, y
9594  //
9595  // mov r1, r0
9596  // cmp r1, x
9597  // mov r0, x
9598  // movne r0, y
9599  // to
9600  // cmp r0, x
9601  // movne r0, y
9602  /// FIXME: Turn this into a target neutral optimization?
9603  SDValue Res;
9604  if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
9605  Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
9606  N->getOperand(3), Cmp);
9607  } else if (CC == ARMCC::EQ && TrueVal == RHS) {
9608  SDValue ARMcc;
9609  SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
9610  Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9611  N->getOperand(3), NewCmp);
9612  }
9613 
9614  if (Res.getNode()) {
9615  APInt KnownZero, KnownOne;
9616  DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
9617  // Capture demanded bits information that would be otherwise lost.
9618  if (KnownZero == 0xfffffffe)
9619  Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9620  DAG.getValueType(MVT::i1));
9621  else if (KnownZero == 0xffffff00)
9622  Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9623  DAG.getValueType(MVT::i8));
9624  else if (KnownZero == 0xffff0000)
9625  Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9626  DAG.getValueType(MVT::i16));
9627  }
9628 
9629  return Res;
9630 }
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
SDNode * getNode() const
get the SDNode which holds the desired result
const SDValue & getOperand(unsigned i) const
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const
unsigned getOpcode() const
Class for arbitrary precision integers.
Definition: APInt.h:75
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getValueType(EVT)
SDValue ARMTargetLowering::PerformDAGCombine ( SDNode N,
DAGCombinerInfo DCI 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 9632 of file ARMISelLowering.cpp.

9633  {
9634  switch (N->getOpcode()) {
9635  default: break;
9636  case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
9637  case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
9638  case ISD::SUB: return PerformSUBCombine(N, DCI);
9639  case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
9640  case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
9641  case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
9642  case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
9643  case ARMISD::BFI: return PerformBFICombine(N, DCI);
9644  case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
9645  case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
9646  case ISD::STORE: return PerformSTORECombine(N, DCI);
9647  case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
9648  case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
9649  case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
9650  case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
9651  case ISD::FP_TO_SINT:
9652  case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
9653  case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
9654  case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
9655  case ISD::SHL:
9656  case ISD::SRA:
9657  case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
9658  case ISD::SIGN_EXTEND:
9659  case ISD::ZERO_EXTEND:
9660  case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
9661  case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
9662  case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
9663  case ARMISD::VLD2DUP:
9664  case ARMISD::VLD3DUP:
9665  case ARMISD::VLD4DUP:
9666  return CombineBaseUpdate(N, DCI);
9667  case ARMISD::BUILD_VECTOR:
9668  return PerformARMBUILD_VECTORCombine(N, DCI);
9669  case ISD::INTRINSIC_VOID:
9671  switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9672  case Intrinsic::arm_neon_vld1:
9673  case Intrinsic::arm_neon_vld2:
9674  case Intrinsic::arm_neon_vld3:
9675  case Intrinsic::arm_neon_vld4:
9676  case Intrinsic::arm_neon_vld2lane:
9677  case Intrinsic::arm_neon_vld3lane:
9678  case Intrinsic::arm_neon_vld4lane:
9679  case Intrinsic::arm_neon_vst1:
9680  case Intrinsic::arm_neon_vst2:
9681  case Intrinsic::arm_neon_vst3:
9682  case Intrinsic::arm_neon_vst4:
9683  case Intrinsic::arm_neon_vst2lane:
9684  case Intrinsic::arm_neon_vst3lane:
9685  case Intrinsic::arm_neon_vst4lane:
9686  return CombineBaseUpdate(N, DCI);
9687  default: break;
9688  }
9689  break;
9690  }
9691  return SDValue();
9692 }
static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG)
PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue PerformVMOVRRDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue PerformInsertEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
unsigned getOpcode() const
const SDValue & getOperand(unsigned Num) const
static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue PerformANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue CombineBaseUpdate(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue PerformVCVTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG)
static SDValue PerformADDCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue PerformMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG)
static SDValue PerformADDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue PerformBFICombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const
PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
static SDValue PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
static SDValue PerformVDUPLANECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue PerformORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
PerformORCombine - Target-specific dag combine xforms for ISD::OR.
static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
const ARMSubtarget * Subtarget
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
static SDValue PerformXORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
static SDValue PerformVDIVCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue PerformBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue PerformSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
virtual SDValue llvm::TargetLowering::prepareVolatileOrAtomicLoad ( SDValue  Chain,
SDLoc  DL,
SelectionDAG DAG 
) const
inlinevirtualinherited

This callback is used to prepare for a volatile or atomic load. It takes a chain node as input and returns the chain for the load itself.

Having a callback like this is necessary for targets like SystemZ, which allows a CPU to reuse the result of a previous load indefinitely, even if a cache-coherent store is performed by another CPU. The default implementation does nothing.

Reimplemented in llvm::SystemZTargetLowering.

Definition at line 2355 of file TargetLowering.h.

2356  {
2357  return Chain;
2358  }
SDValue ARMTargetLowering::ReconstructShuffle ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5119 of file ARMISelLowering.cpp.

5120  {
5121  SDLoc dl(Op);
5122  EVT VT = Op.getValueType();
5123  unsigned NumElts = VT.getVectorNumElements();
5124 
5125  SmallVector<SDValue, 2> SourceVecs;
5126  SmallVector<unsigned, 2> MinElts;
5127  SmallVector<unsigned, 2> MaxElts;
5128 
5129  for (unsigned i = 0; i < NumElts; ++i) {
5130  SDValue V = Op.getOperand(i);
5131  if (V.getOpcode() == ISD::UNDEF)
5132  continue;
5133  else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
5134  // A shuffle can only come from building a vector from various
5135  // elements of other vectors.
5136  return SDValue();
5137  } else if (V.getOperand(0).getValueType().getVectorElementType() !=
5138  VT.getVectorElementType()) {
5139  // This code doesn't know how to handle shuffles where the vector
5140  // element types do not match (this happens because type legalization
5141  // promotes the return type of EXTRACT_VECTOR_ELT).
5142  // FIXME: It might be appropriate to extend this code to handle
5143  // mismatched types.
5144  return SDValue();
5145  }
5146 
5147  // Record this extraction against the appropriate vector if possible...
5148  SDValue SourceVec = V.getOperand(0);
5149  // If the element number isn't a constant, we can't effectively
5150  // analyze what's going on.
5151  if (!isa<ConstantSDNode>(V.getOperand(1)))
5152  return SDValue();
5153  unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5154  bool FoundSource = false;
5155  for (unsigned j = 0; j < SourceVecs.size(); ++j) {
5156  if (SourceVecs[j] == SourceVec) {
5157  if (MinElts[j] > EltNo)
5158  MinElts[j] = EltNo;
5159  if (MaxElts[j] < EltNo)
5160  MaxElts[j] = EltNo;
5161  FoundSource = true;
5162  break;
5163  }
5164  }
5165 
5166  // Or record a new source if not...
5167  if (!FoundSource) {
5168  SourceVecs.push_back(SourceVec);
5169  MinElts.push_back(EltNo);
5170  MaxElts.push_back(EltNo);
5171  }
5172  }
5173 
5174  // Currently only do something sane when at most two source vectors
5175  // involved.
5176  if (SourceVecs.size() > 2)
5177  return SDValue();
5178 
5179  SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
5180  int VEXTOffsets[2] = {0, 0};
5181 
5182  // This loop extracts the usage patterns of the source vectors
5183  // and prepares appropriate SDValues for a shuffle if possible.
5184  for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5185  if (SourceVecs[i].getValueType() == VT) {
5186  // No VEXT necessary
5187  ShuffleSrcs[i] = SourceVecs[i];
5188  VEXTOffsets[i] = 0;
5189  continue;
5190  } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5191  // It probably isn't worth padding out a smaller vector just to
5192  // break it down again in a shuffle.
5193  return SDValue();
5194  }
5195 
5196  // Since only 64-bit and 128-bit vectors are legal on ARM and
5197  // we've eliminated the other cases...
5198  assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5199  "unexpected vector sizes in ReconstructShuffle");
5200 
5201  if (MaxElts[i] - MinElts[i] >= NumElts) {
5202  // Span too large for a VEXT to cope
5203  return SDValue();
5204  }
5205 
5206  if (MinElts[i] >= NumElts) {
5207  // The extraction can just take the second half
5208  VEXTOffsets[i] = NumElts;
5209  ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5210  SourceVecs[i],
5211  DAG.getIntPtrConstant(NumElts));
5212  } else if (MaxElts[i] < NumElts) {
5213  // The extraction can just take the first half
5214  VEXTOffsets[i] = 0;
5215  ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5216  SourceVecs[i],
5217  DAG.getIntPtrConstant(0));
5218  } else {
5219  // An actual VEXT is needed
5220  VEXTOffsets[i] = MinElts[i];
5221  SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5222  SourceVecs[i],
5223  DAG.getIntPtrConstant(0));
5224  SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5225  SourceVecs[i],
5226  DAG.getIntPtrConstant(NumElts));
5227  ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5228  DAG.getConstant(VEXTOffsets[i], MVT::i32));
5229  }
5230  }
5231 
5232  SmallVector<int, 8> Mask;
5233 
5234  for (unsigned i = 0; i < NumElts; ++i) {
5235  SDValue Entry = Op.getOperand(i);
5236  if (Entry.getOpcode() == ISD::UNDEF) {
5237  Mask.push_back(-1);
5238  continue;
5239  }
5240 
5241  SDValue ExtractVec = Entry.getOperand(0);
5242  int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5243  .getOperand(1))->getSExtValue();
5244  if (ExtractVec == SourceVecs[0]) {
5245  Mask.push_back(ExtractElt - VEXTOffsets[0]);
5246  } else {
5247  Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5248  }
5249  }
5250 
5251  // Final check before we try to produce nonsense...
5252  if (isShuffleMaskLegal(Mask, VT))
5253  return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5254  &Mask[0]);
5255 
5256  return SDValue();
5257 }
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
EVT getVectorElementType() const
Definition: ValueTypes.h:217
SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *MaskElts)
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
bool isShuffleMaskLegal(const SmallVectorImpl< int > &M, EVT VT) const override
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
bool llvm::ARMTargetLowering::RemapAddSubWithFlags ( MachineInstr MI,
MachineBasicBlock BB 
) const
private
void ARMTargetLowering::ReplaceNodeResults ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
) const
overridevirtual

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.

Reimplemented from llvm::TargetLowering.

Definition at line 6277 of file ARMISelLowering.cpp.

6279  {
6280  SDValue Res;
6281  switch (N->getOpcode()) {
6282  default:
6283  llvm_unreachable("Don't know how to custom expand this!");
6284  case ISD::BITCAST:
6285  Res = ExpandBITCAST(N, DAG);
6286  break;
6287  case ISD::SRL:
6288  case ISD::SRA:
6289  Res = Expand64BitShift(N, DAG, Subtarget);
6290  break;
6291  case ISD::READCYCLECOUNTER:
6292  ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6293  return;
6294  }
6295  if (Res.getNode())
6296  Results.push_back(Res);
6297 }
unsigned getOpcode() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
SDNode * getNode() const
get the SDNode which holds the desired result
static void ReplaceREADCYCLECOUNTER(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
const ARMSubtarget * Subtarget
static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG)
static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
virtual void llvm::TargetLoweringBase::resetOperationActions ( )
inlinevirtualinherited

Reset the operation actions based on target options.

Reimplemented in llvm::X86TargetLowering.

Definition at line 959 of file TargetLowering.h.

959 {}
void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  Ty)
inlineprotectedinherited

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.

Definition at line 964 of file TargetLowering.h.

964  {
965  BooleanContents = Ty;
967  }
BooleanContent BooleanFloatContents
BooleanContent BooleanContents
void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  IntTy,
BooleanContent  FloatTy 
)
inlineprotectedinherited

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.

Definition at line 971 of file TargetLowering.h.

971  {
972  BooleanContents = IntTy;
973  BooleanFloatContents = FloatTy;
974  }
BooleanContent BooleanFloatContents
BooleanContent BooleanContents
void llvm::TargetLoweringBase::setBooleanVectorContents ( BooleanContent  Ty)
inlineprotectedinherited

Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. See getBooleanContents.

Definition at line 978 of file TargetLowering.h.

978  {
980  }
BooleanContent BooleanVectorContents
void llvm::TargetLoweringBase::setCmpLibcallCC ( RTLIB::Libcall  Call,
ISD::CondCode  CC 
)
inlineinherited

Override the default CondCode to be used to test the result of the comparison libcall against zero.

Definition at line 1431 of file TargetLowering.h.

1431  {
1432  CmpLibcallCCs[Call] = CC;
1433  }
ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]
void llvm::TargetLoweringBase::setCondCodeAction ( ISD::CondCode  CC,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.

The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit value and the upper 27 bits index into the second dimension of the array to select what 32-bit value to use.

Definition at line 1156 of file TargetLowering.h.

1157  {
1158  assert(VT < MVT::LAST_VALUETYPE &&
1159  (unsigned)CC < array_lengthof(CondCodeActions) &&
1160  "Table isn't big enough!");
1161  /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1162  /// value and the upper 27 bits index into the second dimension of the array
1163  /// to select what 32-bit value to use.
1164  uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1165  CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1166  CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1167  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
void llvm::TargetLoweringBase::setExceptionPointerRegister ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this sets the register that receives the exception address on entry to a landing pad.

Definition at line 1018 of file TargetLowering.h.

1018  {
1020  }
void llvm::TargetLoweringBase::setExceptionSelectorRegister ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this sets the register that receives the exception typeid on entry to a landing pad.

Definition at line 1024 of file TargetLowering.h.

1024  {
1026  }
void llvm::TargetLoweringBase::setHasExtractBitsInsn ( bool  hasExtractInsn = true)
inlineprotectedinherited

Tells the code generator that the target has BitExtract instructions. The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.

Definition at line 1047 of file TargetLowering.h.

1047  {
1048  HasExtractBitsInsn = hasExtractInsn;
1049  }
void llvm::TargetLoweringBase::setHasMultipleConditionRegisters ( bool  hasManyRegs = true)
inlineprotectedinherited

Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.

Definition at line 1039 of file TargetLowering.h.

1039  {
1040  HasMultipleConditionRegisters = hasManyRegs;
1041  }
void llvm::TargetLoweringBase::setIndexedLoadAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.

NOTE: All indexed mode loads are initialized to Expand in TargetLowering.cpp

Definition at line 1131 of file TargetLowering.h.

1132  {
1134  (unsigned)Action < 0xf && "Table isn't big enough!");
1135  // Load action are kept in the upper half.
1136  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1137  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1138  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setIndexedStoreAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.

NOTE: All indexed mode stores are initialized to Expand in TargetLowering.cpp

Definition at line 1145 of file TargetLowering.h.

1146  {
1148  (unsigned)Action < 0xf && "Table isn't big enough!");
1149  // Store action are kept in the lower half.
1150  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1151  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1152  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setInsertFencesForAtomic ( bool  fence)
inlineprotectedinherited

Set if the DAG builder should automatically insert fences and reduce the order of atomic memory operations to Monotonic.

Definition at line 1222 of file TargetLowering.h.

1222  {
1223  InsertFencesForAtomic = fence;
1224  }
void llvm::TargetLoweringBase::setIntDivIsCheap ( bool  isCheap = true)
inlineprotectedinherited

Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide.

Definition at line 1060 of file TargetLowering.h.

1060 { IntDivIsCheap = isCheap; }
void llvm::TargetLoweringBase::setJumpBufAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's required jmp_buf buffer alignment (in bytes); default is 0

Definition at line 1192 of file TargetLowering.h.

1192  {
1194  }
unsigned JumpBufAlignment
The alignment, in bytes, of the target's jmp_buf buffers.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setJumpBufSize ( unsigned  Size)
inlineprotectedinherited

Set the target's required jmp_buf buffer size (in bytes); default is 200.

Definition at line 1186 of file TargetLowering.h.

1186  {
1187  JumpBufSize = Size;
1188  }
unsigned JumpBufSize
The size, in bytes, of the target's jmp_buf buffers.
void llvm::TargetLoweringBase::setJumpIsExpensive ( bool  isExpensive = true)
inlineprotectedinherited

Tells the code generator not to expand sequence of operations into a separate sequences that increases the amount of flow control.

Definition at line 1053 of file TargetLowering.h.

1053  {
1054  JumpIsExpensive = isExpensive;
1055  }
void llvm::TargetLoweringBase::setLibcallCallingConv ( RTLIB::Libcall  Call,
CallingConv::ID  CC 
)
inlineinherited

Set the CallingConv that should be used for the specified libcall.

Definition at line 1442 of file TargetLowering.h.

1442  {
1443  LibcallCallingConvs[Call] = CC;
1444  }
CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]
Stores the CallingConv that should be used for each libcall.
void llvm::TargetLoweringBase::setLibcallName ( RTLIB::Libcall  Call,
const char *  Name 
)
inlineinherited

Rename the default libcall routine name for the specified libcall.

Definition at line 1420 of file TargetLowering.h.

1420  {
1422  }
const char * LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]
Stores the name each libcall.
void llvm::TargetLoweringBase::setLoadExtAction ( unsigned  ExtType,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified load with extension does not work with the specified type and indicate what to do about it.

Definition at line 1110 of file TargetLowering.h.

1111  {
1113  "Table isn't big enough!");
1114  LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1115  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
void llvm::TargetLoweringBase::setMinFunctionAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's minimum function alignment (in log2(bytes))

Definition at line 1197 of file TargetLowering.h.

1197  {
1199  }
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setMinimumJumpTableEntries ( int  Val)
inlineprotectedinherited

Indicate the number of blocks to generate jump tables rather than if sequence.

Definition at line 1006 of file TargetLowering.h.

1006  {
1008  }
int MinimumJumpTableEntries
Number of blocks threshold to use jump tables.
void llvm::TargetLoweringBase::setMinStackArgumentAlignment ( unsigned  Align)
inlineprotectedinherited

Set the minimum stack alignment of an argument (in log2(bytes)).

Definition at line 1216 of file TargetLowering.h.

1216  {
1218  }
unsigned MinStackArgumentAlignment
The minimum alignment that any argument on the stack needs to have.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setOperationAction ( unsigned  Op,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified operation does not work with the specified type and indicate what to do about it.

Definition at line 1102 of file TargetLowering.h.

1103  {
1104  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1105  OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1106  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
void llvm::TargetLoweringBase::setPow2DivIsCheap ( bool  isCheap = true)
inlineprotectedinherited

Tells the code generator that it shouldn't generate srl/add/sra for a signed divide by power of two, and let the target handle it.

Definition at line 1069 of file TargetLowering.h.

1069 { Pow2DivIsCheap = isCheap; }
void llvm::TargetLoweringBase::setPrefFunctionAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's preferred function alignment. This should be set if there is a performance benefit to higher-than-minimum alignment (in log2(bytes))

Definition at line 1204 of file TargetLowering.h.

1204  {
1206  }
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setPrefLoopAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's preferred loop alignment. Default alignment is zero, it means the target does not care about loop alignment. The alignment is specified in log2(bytes).

Definition at line 1211 of file TargetLowering.h.

1211  {
1213  }
unsigned PrefLoopAlignment
The preferred loop alignment.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setSchedulingPreference ( Sched::Preference  Pref)
inlineprotectedinherited

Specify the target scheduling preference.

Definition at line 983 of file TargetLowering.h.

983  {
984  SchedPreferenceInfo = Pref;
985  }
Sched::Preference SchedPreferenceInfo
void llvm::TargetLoweringBase::setSelectIsExpensive ( bool  isExpensive = true)
inlineprotectedinherited

Tells the code generator not to expand operations into sequences that use the select operations if possible.

Definition at line 1030 of file TargetLowering.h.

1030  {
1031  SelectIsExpensive = isExpensive;
1032  }
void llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 1012 of file TargetLowering.h.

1012  {
1014  }
unsigned StackPointerRegisterToSaveRestore
void llvm::TargetLoweringBase::setSupportJumpTables ( bool  Val)
inlineprotectedinherited

Indicate whether the target can generate code for jump tables.

Definition at line 1000 of file TargetLowering.h.

1000  {
1001  SupportJumpTables = Val;
1002  }
void llvm::TargetLoweringBase::setTargetDAGCombine ( ISD::NodeType  NT)
inlineprotectedinherited

Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.

Definition at line 1180 of file TargetLowering.h.

1180  {
1181  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1182  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1183  }
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setTruncStoreAction ( MVT  ValVT,
MVT  MemVT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.

Definition at line 1119 of file TargetLowering.h.

1120  {
1121  assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1122  "Table isn't big enough!");
1123  TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1124  }
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
void ARMTargetLowering::SetupEntryBlockForSjLj ( MachineInstr MI,
MachineBasicBlock MBB,
MachineBasicBlock DispatchBB,
int  FI 
) const
private

SetupEntryBlockForSjLj - Insert code into the entry block that creates and registers the function context.

Definition at line 6306 of file ARMISelLowering.cpp.

6307  {
6309  DebugLoc dl = MI->getDebugLoc();
6310  MachineFunction *MF = MBB->getParent();
6311  MachineRegisterInfo *MRI = &MF->getRegInfo();
6312  MachineConstantPool *MCP = MF->getConstantPool();
6313  ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6314  const Function *F = MF->getFunction();
6315 
6316  bool isThumb = Subtarget->isThumb();
6317  bool isThumb2 = Subtarget->isThumb2();
6318 
6319  unsigned PCLabelId = AFI->createPICLabelUId();
6320  unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6321  ARMConstantPoolValue *CPV =
6322  ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6323  unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6324 
6325  const TargetRegisterClass *TRC = isThumb ?
6326  (const TargetRegisterClass*)&ARM::tGPRRegClass :
6327  (const TargetRegisterClass*)&ARM::GPRRegClass;
6328 
6329  // Grab constant pool and fixed stack memory operands.
6330  MachineMemOperand *CPMMO =
6333 
6334  MachineMemOperand *FIMMOSt =
6337 
6338  // Load the address of the dispatch MBB into the jump buffer.
6339  if (isThumb2) {
6340  // Incoming value: jbuf
6341  // ldr.n r5, LCPI1_1
6342  // orr r5, r5, #1
6343  // add r5, pc
6344  // str r5, [$jbuf, #+4] ; &jbuf[1]
6345  unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6346  AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6347  .addConstantPoolIndex(CPI)
6348  .addMemOperand(CPMMO));
6349  // Set the low bit because of thumb mode.
6350  unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6351  AddDefaultCC(
6352  AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6353  .addReg(NewVReg1, RegState::Kill)
6354  .addImm(0x01)));
6355  unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6356  BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6357  .addReg(NewVReg2, RegState::Kill)
6358  .addImm(PCLabelId);
6359  AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6360  .addReg(NewVReg3, RegState::Kill)
6361  .addFrameIndex(FI)
6362  .addImm(36) // &jbuf[1] :: pc
6363  .addMemOperand(FIMMOSt));
6364  } else if (isThumb) {
6365  // Incoming value: jbuf
6366  // ldr.n r1, LCPI1_4
6367  // add r1, pc
6368  // mov r2, #1
6369  // orrs r1, r2
6370  // add r2, $jbuf, #+4 ; &jbuf[1]
6371  // str r1, [r2]
6372  unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6373  AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6374  .addConstantPoolIndex(CPI)
6375  .addMemOperand(CPMMO));
6376  unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6377  BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6378  .addReg(NewVReg1, RegState::Kill)
6379  .addImm(PCLabelId);
6380  // Set the low bit because of thumb mode.
6381  unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6382  AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6383  .addReg(ARM::CPSR, RegState::Define)
6384  .addImm(1));
6385  unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6386  AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6387  .addReg(ARM::CPSR, RegState::Define)
6388  .addReg(NewVReg2, RegState::Kill)
6389  .addReg(NewVReg3, RegState::Kill));
6390  unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6391  AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
6392  .addFrameIndex(FI)
6393  .addImm(36)); // &jbuf[1] :: pc
6394  AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6395  .addReg(NewVReg4, RegState::Kill)
6396  .addReg(NewVReg5, RegState::Kill)
6397  .addImm(0)
6398  .addMemOperand(FIMMOSt));
6399  } else {
6400  // Incoming value: jbuf
6401  // ldr r1, LCPI1_1
6402  // add r1, pc, r1
6403  // str r1, [$jbuf, #+4] ; &jbuf[1]
6404  unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6405  AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6406  .addConstantPoolIndex(CPI)
6407  .addImm(0)
6408  .addMemOperand(CPMMO));
6409  unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6410  AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6411  .addReg(NewVReg1, RegState::Kill)
6412  .addImm(PCLabelId));
6413  AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6414  .addReg(NewVReg2, RegState::Kill)
6415  .addFrameIndex(FI)
6416  .addImm(36) // &jbuf[1] :: pc
6417  .addMemOperand(FIMMOSt));
6418  }
6419 }
The memory access reads data.
const MachineFunction * getParent() const
The machine constant pool.
The memory access writes data.
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
F(f)
const Function * getFunction() const
static MachinePointerInfo getConstantPool()
static bool isThumb(const MCSubtargetInfo &STI)
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const HexagonInstrInfo * TII
bool isThumb() const
Definition: ARMSubtarget.h:400
const MachineInstrBuilder & addImm(int64_t Val) const
MachineConstantPool * getConstantPool()
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
static ARMConstantPoolMBB * Create(LLVMContext &C, const MachineBasicBlock *mbb, unsigned ID, unsigned char PCAdj)
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
virtual const TargetInstrInfo * getInstrInfo() const
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
const ARMSubtarget * Subtarget
const MachineInstrBuilder & addFrameIndex(int Idx) const
MachineRegisterInfo & getRegInfo()
bool isThumb2() const
Definition: ARMSubtarget.h:402
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
void llvm::TargetLoweringBase::setUseUnderscoreLongJmp ( bool  Val)
inlineprotectedinherited

Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. Defaults to false.

Definition at line 995 of file TargetLowering.h.

995  {
996  UseUnderscoreLongJmp = Val;
997  }
void llvm::TargetLoweringBase::setUseUnderscoreSetJmp ( bool  Val)
inlineprotectedinherited

Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. Defaults to false.

Definition at line 989 of file TargetLowering.h.

989  {
990  UseUnderscoreSetJmp = Val;
991  }
bool ARMTargetLowering::shouldConvertConstantLoadToIntImm ( const APInt Imm,
Type Ty 
) const
overridevirtual

Returns true if it is beneficial to convert a load of a constant to just the constant itself.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10778 of file ARMISelLowering.cpp.

10779  {
10780  assert(Ty->isIntegerTy());
10781 
10782  unsigned Bits = Ty->getPrimitiveSizeInBits();
10783  if (Bits == 0 || Bits > 32)
10784  return false;
10785  return true;
10786 }
assert(Globals.size() > 1)
bool isIntegerTy() const
Definition: Type.h:193
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
bool ARMTargetLowering::shouldExpandAtomicInIR ( Instruction Inst) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10788 of file ARMISelLowering.cpp.

10788  {
10789  // Loads and stores less than 64-bits are already atomic; ones above that
10790  // are doomed anyway, so defer to the default libcall and blame the OS when
10791  // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
10792  // anything for those.
10793  bool IsMClass = Subtarget->isMClass();
10794  if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
10795  unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
10796  return Size == 64 && !IsMClass;
10797  } else if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
10798  return LI->getType()->getPrimitiveSizeInBits() == 64 && !IsMClass;
10799  }
10800 
10801  // For the real atomic operations, we have ldrex/strex up to 32 bits,
10802  // and up to 64 bits on the non-M profiles
10803  unsigned AtomicLimit = IsMClass ? 32 : 64;
10804  return Inst->getType()->getPrimitiveSizeInBits() <= AtomicLimit;
10805 }
LoopInfoBase< BlockT, LoopT > * LI
Definition: LoopInfoImpl.h:412
bool isMClass() const
Definition: ARMSubtarget.h:404
Type * getType() const
Definition: Value.h:215
const ARMSubtarget * Subtarget
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
virtual bool llvm::TargetLoweringBase::shouldExpandBuildVectorWithShuffles ( EVT  ,
unsigned  DefinedValues 
) const
inlinevirtualinherited

Reimplemented in llvm::PPCTargetLowering.

Definition at line 208 of file TargetLowering.h.

209  {
210  return DefinedValues < 3;
211  }
virtual bool llvm::TargetLoweringBase::ShouldShrinkFPConstant ( EVT  ) const
inlinevirtualinherited

If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

Reimplemented in llvm::X86TargetLowering, llvm::SparcTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 726 of file TargetLowering.h.

726 { return true; }
bool TargetLowering::SimplifyDemandedBits ( SDValue  Op,
const APInt DemandedMask,
APInt KnownZero,
APInt KnownOne,
TargetLoweringOpt TLO,
unsigned  Depth = 0 
) const
inherited

Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.

SimplifyDemandedBits - Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.

Definition at line 372 of file TargetLowering.cpp.

377  {
378  unsigned BitWidth = DemandedMask.getBitWidth();
379  assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
380  "Mask size mismatches value type size!");
381  APInt NewMask = DemandedMask;
382  SDLoc dl(Op);
383 
384  // Don't know anything.
385  KnownZero = KnownOne = APInt(BitWidth, 0);
386 
387  // Other users may use these bits.
388  if (!Op.getNode()->hasOneUse()) {
389  if (Depth != 0) {
390  // If not at the root, Just compute the KnownZero/KnownOne bits to
391  // simplify things downstream.
392  TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
393  return false;
394  }
395  // If this is the root being simplified, allow it to have multiple uses,
396  // just set the NewMask to all bits.
397  NewMask = APInt::getAllOnesValue(BitWidth);
398  } else if (DemandedMask == 0) {
399  // Not demanding any bits from Op.
400  if (Op.getOpcode() != ISD::UNDEF)
401  return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
402  return false;
403  } else if (Depth == 6) { // Limit search depth.
404  return false;
405  }
406 
407  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
408  switch (Op.getOpcode()) {
409  case ISD::Constant:
410  // We know all of the bits for a constant!
411  KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
412  KnownZero = ~KnownOne;
413  return false; // Don't fall through, will infinitely loop.
414  case ISD::AND:
415  // If the RHS is a constant, check to see if the LHS would be zero without
416  // using the bits from the RHS. Below, we use knowledge about the RHS to
417  // simplify the LHS, here we're using information from the LHS to simplify
418  // the RHS.
419  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
420  APInt LHSZero, LHSOne;
421  // Do not increment Depth here; that can cause an infinite loop.
422  TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
423  // If the LHS already has zeros where RHSC does, this and is dead.
424  if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
425  return TLO.CombineTo(Op, Op.getOperand(0));
426  // If any of the set bits in the RHS are known zero on the LHS, shrink
427  // the constant.
428  if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
429  return true;
430  }
431 
432  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
433  KnownOne, TLO, Depth+1))
434  return true;
435  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
436  if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
437  KnownZero2, KnownOne2, TLO, Depth+1))
438  return true;
439  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
440 
441  // If all of the demanded bits are known one on one side, return the other.
442  // These bits cannot contribute to the result of the 'and'.
443  if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
444  return TLO.CombineTo(Op, Op.getOperand(0));
445  if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
446  return TLO.CombineTo(Op, Op.getOperand(1));
447  // If all of the demanded bits in the inputs are known zeros, return zero.
448  if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
449  return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
450  // If the RHS is a constant, see if we can simplify it.
451  if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
452  return true;
453  // If the operation can be done in a smaller type, do so.
454  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
455  return true;
456 
457  // Output known-1 bits are only known if set in both the LHS & RHS.
458  KnownOne &= KnownOne2;
459  // Output known-0 are known to be clear if zero in either the LHS | RHS.
460  KnownZero |= KnownZero2;
461  break;
462  case ISD::OR:
463  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
464  KnownOne, TLO, Depth+1))
465  return true;
466  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
467  if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
468  KnownZero2, KnownOne2, TLO, Depth+1))
469  return true;
470  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
471 
472  // If all of the demanded bits are known zero on one side, return the other.
473  // These bits cannot contribute to the result of the 'or'.
474  if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
475  return TLO.CombineTo(Op, Op.getOperand(0));
476  if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
477  return TLO.CombineTo(Op, Op.getOperand(1));
478  // If all of the potentially set bits on one side are known to be set on
479  // the other side, just use the 'other' side.
480  if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
481  return TLO.CombineTo(Op, Op.getOperand(0));
482  if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
483  return TLO.CombineTo(Op, Op.getOperand(1));
484  // If the RHS is a constant, see if we can simplify it.
485  if (TLO.ShrinkDemandedConstant(Op, NewMask))
486  return true;
487  // If the operation can be done in a smaller type, do so.
488  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
489  return true;
490 
491  // Output known-0 bits are only known if clear in both the LHS & RHS.
492  KnownZero &= KnownZero2;
493  // Output known-1 are known to be set if set in either the LHS | RHS.
494  KnownOne |= KnownOne2;
495  break;
496  case ISD::XOR:
497  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
498  KnownOne, TLO, Depth+1))
499  return true;
500  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
501  if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
502  KnownOne2, TLO, Depth+1))
503  return true;
504  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
505 
506  // If all of the demanded bits are known zero on one side, return the other.
507  // These bits cannot contribute to the result of the 'xor'.
508  if ((KnownZero & NewMask) == NewMask)
509  return TLO.CombineTo(Op, Op.getOperand(0));
510  if ((KnownZero2 & NewMask) == NewMask)
511  return TLO.CombineTo(Op, Op.getOperand(1));
512  // If the operation can be done in a smaller type, do so.
513  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
514  return true;
515 
516  // If all of the unknown bits are known to be zero on one side or the other
517  // (but not both) turn this into an *inclusive* or.
518  // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
519  if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
520  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
521  Op.getOperand(0),
522  Op.getOperand(1)));
523 
524  // Output known-0 bits are known if clear or set in both the LHS & RHS.
525  KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
526  // Output known-1 are known to be set if set in only one of the LHS, RHS.
527  KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
528 
529  // If all of the demanded bits on one side are known, and all of the set
530  // bits on that side are also known to be set on the other side, turn this
531  // into an AND, as we know the bits will be cleared.
532  // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
533  // NB: it is okay if more bits are known than are requested
534  if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
535  if (KnownOne == KnownOne2) { // set bits are the same on both sides
536  EVT VT = Op.getValueType();
537  SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
538  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
539  Op.getOperand(0), ANDC));
540  }
541  }
542 
543  // If the RHS is a constant, see if we can simplify it.
544  // for XOR, we prefer to force bits to 1 if they will make a -1.
545  // if we can't force bits, try to shrink constant
546  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
547  APInt Expanded = C->getAPIntValue() | (~NewMask);
548  // if we can expand it to have all bits set, do it
549  if (Expanded.isAllOnesValue()) {
550  if (Expanded != C->getAPIntValue()) {
551  EVT VT = Op.getValueType();
552  SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
553  TLO.DAG.getConstant(Expanded, VT));
554  return TLO.CombineTo(Op, New);
555  }
556  // if it already has all the bits set, nothing to change
557  // but don't shrink either!
558  } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
559  return true;
560  }
561  }
562 
563  KnownZero = KnownZeroOut;
564  KnownOne = KnownOneOut;
565  break;
566  case ISD::SELECT:
567  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
568  KnownOne, TLO, Depth+1))
569  return true;
570  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
571  KnownOne2, TLO, Depth+1))
572  return true;
573  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
574  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
575 
576  // If the operands are constants, see if we can simplify them.
577  if (TLO.ShrinkDemandedConstant(Op, NewMask))
578  return true;
579 
580  // Only known if known in both the LHS and RHS.
581  KnownOne &= KnownOne2;
582  KnownZero &= KnownZero2;
583  break;
584  case ISD::SELECT_CC:
585  if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
586  KnownOne, TLO, Depth+1))
587  return true;
588  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
589  KnownOne2, TLO, Depth+1))
590  return true;
591  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
592  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
593 
594  // If the operands are constants, see if we can simplify them.
595  if (TLO.ShrinkDemandedConstant(Op, NewMask))
596  return true;
597 
598  // Only known if known in both the LHS and RHS.
599  KnownOne &= KnownOne2;
600  KnownZero &= KnownZero2;
601  break;
602  case ISD::SHL:
603  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
604  unsigned ShAmt = SA->getZExtValue();
605  SDValue InOp = Op.getOperand(0);
606 
607  // If the shift count is an invalid immediate, don't do anything.
608  if (ShAmt >= BitWidth)
609  break;
610 
611  // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
612  // single shift. We can do this if the bottom bits (which are shifted
613  // out) are never demanded.
614  if (InOp.getOpcode() == ISD::SRL &&
615  isa<ConstantSDNode>(InOp.getOperand(1))) {
616  if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
617  unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
618  unsigned Opc = ISD::SHL;
619  int Diff = ShAmt-C1;
620  if (Diff < 0) {
621  Diff = -Diff;
622  Opc = ISD::SRL;
623  }
624 
625  SDValue NewSA =
626  TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
627  EVT VT = Op.getValueType();
628  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
629  InOp.getOperand(0), NewSA));
630  }
631  }
632 
633  if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
634  KnownZero, KnownOne, TLO, Depth+1))
635  return true;
636 
637  // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
638  // are not demanded. This will likely allow the anyext to be folded away.
639  if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
640  SDValue InnerOp = InOp.getNode()->getOperand(0);
641  EVT InnerVT = InnerOp.getValueType();
642  unsigned InnerBits = InnerVT.getSizeInBits();
643  if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
644  isTypeDesirableForOp(ISD::SHL, InnerVT)) {
645  EVT ShTy = getShiftAmountTy(InnerVT);
646  if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
647  ShTy = InnerVT;
648  SDValue NarrowShl =
649  TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
650  TLO.DAG.getConstant(ShAmt, ShTy));
651  return
652  TLO.CombineTo(Op,
653  TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
654  NarrowShl));
655  }
656  // Repeat the SHL optimization above in cases where an extension
657  // intervenes: (shl (anyext (shr x, c1)), c2) to
658  // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
659  // aren't demanded (as above) and that the shifted upper c1 bits of
660  // x aren't demanded.
661  if (InOp.hasOneUse() &&
662  InnerOp.getOpcode() == ISD::SRL &&
663  InnerOp.hasOneUse() &&
664  isa<ConstantSDNode>(InnerOp.getOperand(1))) {
665  uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
666  ->getZExtValue();
667  if (InnerShAmt < ShAmt &&
668  InnerShAmt < InnerBits &&
669  NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
670  NewMask.trunc(ShAmt) == 0) {
671  SDValue NewSA =
672  TLO.DAG.getConstant(ShAmt - InnerShAmt,
673  Op.getOperand(1).getValueType());
674  EVT VT = Op.getValueType();
675  SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
676  InnerOp.getOperand(0));
677  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
678  NewExt, NewSA));
679  }
680  }
681  }
682 
683  KnownZero <<= SA->getZExtValue();
684  KnownOne <<= SA->getZExtValue();
685  // low bits known zero.
686  KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
687  }
688  break;
689  case ISD::SRL:
690  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
691  EVT VT = Op.getValueType();
692  unsigned ShAmt = SA->getZExtValue();
693  unsigned VTSize = VT.getSizeInBits();
694  SDValue InOp = Op.getOperand(0);
695 
696  // If the shift count is an invalid immediate, don't do anything.
697  if (ShAmt >= BitWidth)
698  break;
699 
700  // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
701  // single shift. We can do this if the top bits (which are shifted out)
702  // are never demanded.
703  if (InOp.getOpcode() == ISD::SHL &&
704  isa<ConstantSDNode>(InOp.getOperand(1))) {
705  if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
706  unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
707  unsigned Opc = ISD::SRL;
708  int Diff = ShAmt-C1;
709  if (Diff < 0) {
710  Diff = -Diff;
711  Opc = ISD::SHL;
712  }
713 
714  SDValue NewSA =
715  TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
716  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
717  InOp.getOperand(0), NewSA));
718  }
719  }
720 
721  // Compute the new bits that are at the top now.
722  if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
723  KnownZero, KnownOne, TLO, Depth+1))
724  return true;
725  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
726  KnownZero = KnownZero.lshr(ShAmt);
727  KnownOne = KnownOne.lshr(ShAmt);
728 
729  APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
730  KnownZero |= HighBits; // High bits known zero.
731  }
732  break;
733  case ISD::SRA:
734  // If this is an arithmetic shift right and only the low-bit is set, we can
735  // always convert this into a logical shr, even if the shift amount is
736  // variable. The low bit of the shift cannot be an input sign bit unless
737  // the shift amount is >= the size of the datatype, which is undefined.
738  if (NewMask == 1)
739  return TLO.CombineTo(Op,
740  TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
741  Op.getOperand(0), Op.getOperand(1)));
742 
743  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
744  EVT VT = Op.getValueType();
745  unsigned ShAmt = SA->getZExtValue();
746 
747  // If the shift count is an invalid immediate, don't do anything.
748  if (ShAmt >= BitWidth)
749  break;
750 
751  APInt InDemandedMask = (NewMask << ShAmt);
752 
753  // If any of the demanded bits are produced by the sign extension, we also
754  // demand the input sign bit.
755  APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
756  if (HighBits.intersects(NewMask))
757  InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
758 
759  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
760  KnownZero, KnownOne, TLO, Depth+1))
761  return true;
762  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
763  KnownZero = KnownZero.lshr(ShAmt);
764  KnownOne = KnownOne.lshr(ShAmt);
765 
766  // Handle the sign bit, adjusted to where it is now in the mask.
767  APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
768 
769  // If the input sign bit is known to be zero, or if none of the top bits
770  // are demanded, turn this into an unsigned shift right.
771  if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
772  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
773  Op.getOperand(0),
774  Op.getOperand(1)));
775 
776  int Log2 = NewMask.exactLogBase2();
777  if (Log2 >= 0) {
778  // The bit must come from the sign.
779  SDValue NewSA =
780  TLO.DAG.getConstant(BitWidth - 1 - Log2,
781  Op.getOperand(1).getValueType());
782  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
783  Op.getOperand(0), NewSA));
784  }
785 
786  if (KnownOne.intersects(SignBit))
787  // New bits are known one.
788  KnownOne |= HighBits;
789  }
790  break;
791  case ISD::SIGN_EXTEND_INREG: {
792  EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
793 
794  APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
795  // If we only care about the highest bit, don't bother shifting right.
796  if (MsbMask == DemandedMask) {
797  unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
798  SDValue InOp = Op.getOperand(0);
799 
800  // Compute the correct shift amount type, which must be getShiftAmountTy
801  // for scalar types after legalization.
802  EVT ShiftAmtTy = Op.getValueType();
803  if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
804  ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
805 
806  SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
807  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
808  Op.getValueType(), InOp, ShiftAmt));
809  }
810 
811  // Sign extension. Compute the demanded bits in the result that are not
812  // present in the input.
813  APInt NewBits =
814  APInt::getHighBitsSet(BitWidth,
815  BitWidth - ExVT.getScalarType().getSizeInBits());
816 
817  // If none of the extended bits are demanded, eliminate the sextinreg.
818  if ((NewBits & NewMask) == 0)
819  return TLO.CombineTo(Op, Op.getOperand(0));
820 
821  APInt InSignBit =
822  APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
823  APInt InputDemandedBits =
824  APInt::getLowBitsSet(BitWidth,
825  ExVT.getScalarType().getSizeInBits()) &
826  NewMask;
827 
828  // Since the sign extended bits are demanded, we know that the sign
829  // bit is demanded.
830  InputDemandedBits |= InSignBit;
831 
832  if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
833  KnownZero, KnownOne, TLO, Depth+1))
834  return true;
835  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
836 
837  // If the sign bit of the input is known set or clear, then we know the
838  // top bits of the result.
839 
840  // If the input sign bit is known zero, convert this into a zero extension.
841  if (KnownZero.intersects(InSignBit))
842  return TLO.CombineTo(Op,
843  TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
844 
845  if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
846  KnownOne |= NewBits;
847  KnownZero &= ~NewBits;
848  } else { // Input sign bit unknown
849  KnownZero &= ~NewBits;
850  KnownOne &= ~NewBits;
851  }
852  break;
853  }
854  case ISD::BUILD_PAIR: {
855  EVT HalfVT = Op.getOperand(0).getValueType();
856  unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
857 
858  APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
859  APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
860 
861  APInt KnownZeroLo, KnownOneLo;
862  APInt KnownZeroHi, KnownOneHi;
863 
864  if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
865  KnownOneLo, TLO, Depth + 1))
866  return true;
867 
868  if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
869  KnownOneHi, TLO, Depth + 1))
870  return true;
871 
872  KnownZero = KnownZeroLo.zext(BitWidth) |
873  KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
874 
875  KnownOne = KnownOneLo.zext(BitWidth) |
876  KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
877  break;
878  }
879  case ISD::ZERO_EXTEND: {
880  unsigned OperandBitWidth =
882  APInt InMask = NewMask.trunc(OperandBitWidth);
883 
884  // If none of the top bits are demanded, convert this into an any_extend.
885  APInt NewBits =
886  APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
887  if (!NewBits.intersects(NewMask))
888  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
889  Op.getValueType(),
890  Op.getOperand(0)));
891 
892  if (SimplifyDemandedBits(Op.getOperand(0), InMask,
893  KnownZero, KnownOne, TLO, Depth+1))
894  return true;
895  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
896  KnownZero = KnownZero.zext(BitWidth);
897  KnownOne = KnownOne.zext(BitWidth);
898  KnownZero |= NewBits;
899  break;
900  }
901  case ISD::SIGN_EXTEND: {
902  EVT InVT = Op.getOperand(0).getValueType();
903  unsigned InBits = InVT.getScalarType().getSizeInBits();
904  APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
905  APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
906  APInt NewBits = ~InMask & NewMask;
907 
908  // If none of the top bits are demanded, convert this into an any_extend.
909  if (NewBits == 0)
910  return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
911  Op.getValueType(),
912  Op.getOperand(0)));
913 
914  // Since some of the sign extended bits are demanded, we know that the sign
915  // bit is demanded.
916  APInt InDemandedBits = InMask & NewMask;
917  InDemandedBits |= InSignBit;
918  InDemandedBits = InDemandedBits.trunc(InBits);
919 
920  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
921  KnownOne, TLO, Depth+1))
922  return true;
923  KnownZero = KnownZero.zext(BitWidth);
924  KnownOne = KnownOne.zext(BitWidth);
925 
926  // If the sign bit is known zero, convert this to a zero extend.
927  if (KnownZero.intersects(InSignBit))
928  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
929  Op.getValueType(),
930  Op.getOperand(0)));
931 
932  // If the sign bit is known one, the top bits match.
933  if (KnownOne.intersects(InSignBit)) {
934  KnownOne |= NewBits;
935  assert((KnownZero & NewBits) == 0);
936  } else { // Otherwise, top bits aren't known.
937  assert((KnownOne & NewBits) == 0);
938  assert((KnownZero & NewBits) == 0);
939  }
940  break;
941  }
942  case ISD::ANY_EXTEND: {
943  unsigned OperandBitWidth =
945  APInt InMask = NewMask.trunc(OperandBitWidth);
946  if (SimplifyDemandedBits(Op.getOperand(0), InMask,
947  KnownZero, KnownOne, TLO, Depth+1))
948  return true;
949  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
950  KnownZero = KnownZero.zext(BitWidth);
951  KnownOne = KnownOne.zext(BitWidth);
952  break;
953  }
954  case ISD::TRUNCATE: {
955  // Simplify the input, using demanded bit information, and compute the known
956  // zero/one bits live out.
957  unsigned OperandBitWidth =
959  APInt TruncMask = NewMask.zext(OperandBitWidth);
960  if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
961  KnownZero, KnownOne, TLO, Depth+1))
962  return true;
963  KnownZero = KnownZero.trunc(BitWidth);
964  KnownOne = KnownOne.trunc(BitWidth);
965 
966  // If the input is only used by this truncate, see if we can shrink it based
967  // on the known demanded bits.
968  if (Op.getOperand(0).getNode()->hasOneUse()) {
969  SDValue In = Op.getOperand(0);
970  switch (In.getOpcode()) {
971  default: break;
972  case ISD::SRL:
973  // Shrink SRL by a constant if none of the high bits shifted in are
974  // demanded.
975  if (TLO.LegalTypes() &&
977  // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
978  // undesirable.
979  break;
981  if (!ShAmt)
982  break;
983  SDValue Shift = In.getOperand(1);
984  if (TLO.LegalTypes()) {
985  uint64_t ShVal = ShAmt->getZExtValue();
986  Shift =
987  TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
988  }
989 
990  APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
991  OperandBitWidth - BitWidth);
992  HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
993 
994  if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
995  // None of the shifted in bits are needed. Add a truncate of the
996  // shift input, then shift it.
997  SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
998  Op.getValueType(),
999  In.getOperand(0));
1000  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1001  Op.getValueType(),
1002  NewTrunc,
1003  Shift));
1004  }
1005  break;
1006  }
1007  }
1008 
1009  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1010  break;
1011  }
1012  case ISD::AssertZext: {
1013  // AssertZext demands all of the high bits, plus any of the low bits
1014  // demanded by its users.
1015  EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1016  APInt InMask = APInt::getLowBitsSet(BitWidth,
1017  VT.getSizeInBits());
1018  if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1019  KnownZero, KnownOne, TLO, Depth+1))
1020  return true;
1021  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1022 
1023  KnownZero |= ~InMask & NewMask;
1024  break;
1025  }
1026  case ISD::BITCAST:
1027  // If this is an FP->Int bitcast and if the sign bit is the only
1028  // thing demanded, turn this into a FGETSIGN.
1029  if (!TLO.LegalOperations() &&
1030  !Op.getValueType().isVector() &&
1031  !Op.getOperand(0).getValueType().isVector() &&
1032  NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1034  bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1036  if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1037  EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1038  // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1039  // place. We expect the SHL to be eliminated by other optimizations.
1040  SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1041  unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1042  if (!OpVTLegal && OpVTSizeInBits > 32)
1043  Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1044  unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1045  SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1046  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1047  Op.getValueType(),
1048  Sign, ShAmt));
1049  }
1050  }
1051  break;
1052  case ISD::ADD:
1053  case ISD::MUL:
1054  case ISD::SUB: {
1055  // Add, Sub, and Mul don't demand any bits in positions beyond that
1056  // of the highest bit demanded of them.
1057  APInt LoMask = APInt::getLowBitsSet(BitWidth,
1058  BitWidth - NewMask.countLeadingZeros());
1059  if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1060  KnownOne2, TLO, Depth+1))
1061  return true;
1062  if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1063  KnownOne2, TLO, Depth+1))
1064  return true;
1065  // See if the operation should be performed at a smaller bit width.
1066  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1067  return true;
1068  }
1069  // FALL THROUGH
1070  default:
1071  // Just use computeKnownBits to compute output bits.
1072  TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1073  break;
1074  }
1075 
1076  // If we know the value of all of the demanded bits, return this as a
1077  // constant.
1078  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1079  return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1080 
1081  return false;
1082 }
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
Definition: APInt.h:441
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:448
bool hasOneUse() const
bool hasOneUse() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:526
unsigned getOpcode() const
const SDValue & getOperand(unsigned Num) const
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
double trunc(double x);
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
EVT getShiftAmountTy(EVT LHSTy) const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
EVT getScalarType() const
Definition: ValueTypes.h:211
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
APInt LLVM_ATTRIBUTE_UNUSED_RESULT shl(unsigned shiftAmt) const
Left-shift function.
Definition: APInt.h:852
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:240
assert(Globals.size() > 1)
bool intersects(const APInt &RHS) const
Definition: APInt.h:1140
APInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:920
const SDValue & getOperand(unsigned i) const
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
APInt getLoBits(unsigned numBits) const
Compute an APInt containing numBits lowbits from this APInt.
Definition: APInt.cpp:677
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned getOpcode() const
bool isIntN(unsigned N, int64_t x)
Definition: MathExtras.h:330
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
Definition: APInt.cpp:672
int32_t exactLogBase2() const
Definition: APInt.h:1534
Class for arbitrary precision integers.
Definition: APInt.h:75
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
Definition: APInt.h:493
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:338
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
bool isSimple() const
Definition: ValueTypes.h:95
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:984
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
uint64_t getZExtValue() const
SDValue TargetLowering::SimplifySetCC ( EVT  VT,
SDValue  N0,
SDValue  N1,
ISD::CondCode  Cond,
bool  foldBooleans,
DAGCombinerInfo DCI,
SDLoc  dl 
) const
inherited

Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.

SimplifySetCC - Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.

Definition at line 1206 of file TargetLowering.cpp.

1208  {
1209  SelectionDAG &DAG = DCI.DAG;
1210 
1211  // These setcc operations always fold.
1212  switch (Cond) {
1213  default: break;
1214  case ISD::SETFALSE:
1215  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1216  case ISD::SETTRUE:
1217  case ISD::SETTRUE2: {
1220  return DAG.getConstant(
1221  Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
1222  }
1223  }
1224 
1225  // Ensure that the constant occurs on the RHS, and fold constant
1226  // comparisons.
1227  ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1228  if (isa<ConstantSDNode>(N0.getNode()) &&
1229  (DCI.isBeforeLegalizeOps() ||
1230  isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1231  return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1232 
1233  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1234  const APInt &C1 = N1C->getAPIntValue();
1235 
1236  // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1237  // equality comparison, then we're just comparing whether X itself is
1238  // zero.
1239  if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1240  N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1241  N0.getOperand(1).getOpcode() == ISD::Constant) {
1242  const APInt &ShAmt
1243  = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1244  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1245  ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1246  if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1247  // (srl (ctlz x), 5) == 0 -> X != 0
1248  // (srl (ctlz x), 5) != 1 -> X != 0
1249  Cond = ISD::SETNE;
1250  } else {
1251  // (srl (ctlz x), 5) != 0 -> X == 0
1252  // (srl (ctlz x), 5) == 1 -> X == 0
1253  Cond = ISD::SETEQ;
1254  }
1255  SDValue Zero = DAG.getConstant(0, N0.getValueType());
1256  return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1257  Zero, Cond);
1258  }
1259  }
1260 
1261  SDValue CTPOP = N0;
1262  // Look through truncs that don't change the value of a ctpop.
1263  if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1264  CTPOP = N0.getOperand(0);
1265 
1266  if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1267  (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1268  Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1269  EVT CTVT = CTPOP.getValueType();
1270  SDValue CTOp = CTPOP.getOperand(0);
1271 
1272  // (ctpop x) u< 2 -> (x & x-1) == 0
1273  // (ctpop x) u> 1 -> (x & x-1) != 0
1274  if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1275  SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1276  DAG.getConstant(1, CTVT));
1277  SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1279  return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1280  }
1281 
1282  // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1283  }
1284 
1285  // (zext x) == C --> x == (trunc C)
1286  if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1287  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1288  unsigned MinBits = N0.getValueSizeInBits();
1289  SDValue PreZExt;
1290  if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1291  // ZExt
1292  MinBits = N0->getOperand(0).getValueSizeInBits();
1293  PreZExt = N0->getOperand(0);
1294  } else if (N0->getOpcode() == ISD::AND) {
1295  // DAGCombine turns costly ZExts into ANDs
1296  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1297  if ((C->getAPIntValue()+1).isPowerOf2()) {
1298  MinBits = C->getAPIntValue().countTrailingOnes();
1299  PreZExt = N0->getOperand(0);
1300  }
1301  } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1302  // ZEXTLOAD
1303  if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1304  MinBits = LN0->getMemoryVT().getSizeInBits();
1305  PreZExt = N0;
1306  }
1307  }
1308 
1309  // Make sure we're not losing bits from the constant.
1310  if (MinBits > 0 &&
1311  MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
1312  EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1313  if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1314  // Will get folded away.
1315  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1316  SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1317  return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1318  }
1319  }
1320  }
1321 
1322  // If the LHS is '(and load, const)', the RHS is 0,
1323  // the test is for equality or unsigned, and all 1 bits of the const are
1324  // in the same partial word, see if we can shorten the load.
1325  if (DCI.isBeforeLegalize() &&
1326  !ISD::isSignedIntSetCC(Cond) &&
1327  N0.getOpcode() == ISD::AND && C1 == 0 &&
1328  N0.getNode()->hasOneUse() &&
1329  isa<LoadSDNode>(N0.getOperand(0)) &&
1330  N0.getOperand(0).getNode()->hasOneUse() &&
1331  isa<ConstantSDNode>(N0.getOperand(1))) {
1332  LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1333  APInt bestMask;
1334  unsigned bestWidth = 0, bestOffset = 0;
1335  if (!Lod->isVolatile() && Lod->isUnindexed()) {
1336  unsigned origWidth = N0.getValueType().getSizeInBits();
1337  unsigned maskWidth = origWidth;
1338  // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1339  // 8 bits, but have to be careful...
1340  if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1341  origWidth = Lod->getMemoryVT().getSizeInBits();
1342  const APInt &Mask =
1343  cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1344  for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1345  APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1346  for (unsigned offset=0; offset<origWidth/width; offset++) {
1347  if ((newMask & Mask) == Mask) {
1348  if (!getDataLayout()->isLittleEndian())
1349  bestOffset = (origWidth/width - offset - 1) * (width/8);
1350  else
1351  bestOffset = (uint64_t)offset * (width/8);
1352  bestMask = Mask.lshr(offset * (width/8) * 8);
1353  bestWidth = width;
1354  break;
1355  }
1356  newMask = newMask << width;
1357  }
1358  }
1359  }
1360  if (bestWidth) {
1361  EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1362  if (newVT.isRound()) {
1363  EVT PtrType = Lod->getOperand(1).getValueType();
1364  SDValue Ptr = Lod->getBasePtr();
1365  if (bestOffset != 0)
1366  Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1367  DAG.getConstant(bestOffset, PtrType));
1368  unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1369  SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1370  Lod->getPointerInfo().getWithOffset(bestOffset),
1371  false, false, false, NewAlign);
1372  return DAG.getSetCC(dl, VT,
1373  DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1374  DAG.getConstant(bestMask.trunc(bestWidth),
1375  newVT)),
1376  DAG.getConstant(0LL, newVT), Cond);
1377  }
1378  }
1379  }
1380 
1381  // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1382  if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1383  unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1384 
1385  // If the comparison constant has bits in the upper part, the
1386  // zero-extended value could never match.
1387  if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1388  C1.getBitWidth() - InSize))) {
1389  switch (Cond) {
1390  case ISD::SETUGT:
1391  case ISD::SETUGE:
1392  case ISD::SETEQ: return DAG.getConstant(0, VT);
1393  case ISD::SETULT:
1394  case ISD::SETULE:
1395  case ISD::SETNE: return DAG.getConstant(1, VT);
1396  case ISD::SETGT:
1397  case ISD::SETGE:
1398  // True if the sign bit of C1 is set.
1399  return DAG.getConstant(C1.isNegative(), VT);
1400  case ISD::SETLT:
1401  case ISD::SETLE:
1402  // True if the sign bit of C1 isn't set.
1403  return DAG.getConstant(C1.isNonNegative(), VT);
1404  default:
1405  break;
1406  }
1407  }
1408 
1409  // Otherwise, we can perform the comparison with the low bits.
1410  switch (Cond) {
1411  case ISD::SETEQ:
1412  case ISD::SETNE:
1413  case ISD::SETUGT:
1414  case ISD::SETUGE:
1415  case ISD::SETULT:
1416  case ISD::SETULE: {
1417  EVT newVT = N0.getOperand(0).getValueType();
1418  if (DCI.isBeforeLegalizeOps() ||
1419  (isOperationLegal(ISD::SETCC, newVT) &&
1420  getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1421  EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1422  SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
1423 
1424  SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1425  NewConst, Cond);
1426  return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1427  }
1428  break;
1429  }
1430  default:
1431  break; // todo, be more careful with signed comparisons
1432  }
1433  } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1434  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1435  EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1436  unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1437  EVT ExtDstTy = N0.getValueType();
1438  unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1439 
1440  // If the constant doesn't fit into the number of bits for the source of
1441  // the sign extension, it is impossible for both sides to be equal.
1442  if (C1.getMinSignedBits() > ExtSrcTyBits)
1443  return DAG.getConstant(Cond == ISD::SETNE, VT);
1444 
1445  SDValue ZextOp;
1446  EVT Op0Ty = N0.getOperand(0).getValueType();
1447  if (Op0Ty == ExtSrcTy) {
1448  ZextOp = N0.getOperand(0);
1449  } else {
1450  APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1451  ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1452  DAG.getConstant(Imm, Op0Ty));
1453  }
1454  if (!DCI.isCalledByLegalizer())
1455  DCI.AddToWorklist(ZextOp.getNode());
1456  // Otherwise, make this a use of a zext.
1457  return DAG.getSetCC(dl, VT, ZextOp,
1459  ExtDstTyBits,
1460  ExtSrcTyBits),
1461  ExtDstTy),
1462  Cond);
1463  } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1464  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1465  // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1466  if (N0.getOpcode() == ISD::SETCC &&
1467  isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1468  bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1469  if (TrueWhenTrue)
1470  return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1471  // Invert the condition.
1472  ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1473  CC = ISD::getSetCCInverse(CC,
1474  N0.getOperand(0).getValueType().isInteger());
1475  if (DCI.isBeforeLegalizeOps() ||
1476  isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1477  return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1478  }
1479 
1480  if ((N0.getOpcode() == ISD::XOR ||
1481  (N0.getOpcode() == ISD::AND &&
1482  N0.getOperand(0).getOpcode() == ISD::XOR &&
1483  N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1484  isa<ConstantSDNode>(N0.getOperand(1)) &&
1485  cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1486  // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1487  // can only do this if the top bits are known zero.
1488  unsigned BitWidth = N0.getValueSizeInBits();
1489  if (DAG.MaskedValueIsZero(N0,
1490  APInt::getHighBitsSet(BitWidth,
1491  BitWidth-1))) {
1492  // Okay, get the un-inverted input value.
1493  SDValue Val;
1494  if (N0.getOpcode() == ISD::XOR)
1495  Val = N0.getOperand(0);
1496  else {
1497  assert(N0.getOpcode() == ISD::AND &&
1498  N0.getOperand(0).getOpcode() == ISD::XOR);
1499  // ((X^1)&1)^1 -> X & 1
1500  Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1501  N0.getOperand(0).getOperand(0),
1502  N0.getOperand(1));
1503  }
1504 
1505  return DAG.getSetCC(dl, VT, Val, N1,
1506  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1507  }
1508  } else if (N1C->getAPIntValue() == 1 &&
1509  (VT == MVT::i1 ||
1510  getBooleanContents(N0->getValueType(0)) ==
1512  SDValue Op0 = N0;
1513  if (Op0.getOpcode() == ISD::TRUNCATE)
1514  Op0 = Op0.getOperand(0);
1515 
1516  if ((Op0.getOpcode() == ISD::XOR) &&
1517  Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1518  Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1519  // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1520  Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1521  return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1522  Cond);
1523  }
1524  if (Op0.getOpcode() == ISD::AND &&
1525  isa<ConstantSDNode>(Op0.getOperand(1)) &&
1526  cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1527  // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1528  if (Op0.getValueType().bitsGT(VT))
1529  Op0 = DAG.getNode(ISD::AND, dl, VT,
1530  DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1531  DAG.getConstant(1, VT));
1532  else if (Op0.getValueType().bitsLT(VT))
1533  Op0 = DAG.getNode(ISD::AND, dl, VT,
1534  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1535  DAG.getConstant(1, VT));
1536 
1537  return DAG.getSetCC(dl, VT, Op0,
1538  DAG.getConstant(0, Op0.getValueType()),
1539  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1540  }
1541  if (Op0.getOpcode() == ISD::AssertZext &&
1542  cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1543  return DAG.getSetCC(dl, VT, Op0,
1544  DAG.getConstant(0, Op0.getValueType()),
1545  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1546  }
1547  }
1548 
1549  APInt MinVal, MaxVal;
1550  unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1551  if (ISD::isSignedIntSetCC(Cond)) {
1552  MinVal = APInt::getSignedMinValue(OperandBitSize);
1553  MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1554  } else {
1555  MinVal = APInt::getMinValue(OperandBitSize);
1556  MaxVal = APInt::getMaxValue(OperandBitSize);
1557  }
1558 
1559  // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1560  if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1561  if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1562  // X >= C0 --> X > (C0 - 1)
1563  APInt C = C1 - 1;
1564  ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1565  if ((DCI.isBeforeLegalizeOps() ||
1566  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1567  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1569  return DAG.getSetCC(dl, VT, N0,
1570  DAG.getConstant(C, N1.getValueType()),
1571  NewCC);
1572  }
1573  }
1574 
1575  if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1576  if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1577  // X <= C0 --> X < (C0 + 1)
1578  APInt C = C1 + 1;
1579  ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1580  if ((DCI.isBeforeLegalizeOps() ||
1581  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1582  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1584  return DAG.getSetCC(dl, VT, N0,
1585  DAG.getConstant(C, N1.getValueType()),
1586  NewCC);
1587  }
1588  }
1589 
1590  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1591  return DAG.getConstant(0, VT); // X < MIN --> false
1592  if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1593  return DAG.getConstant(1, VT); // X >= MIN --> true
1594  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1595  return DAG.getConstant(0, VT); // X > MAX --> false
1596  if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1597  return DAG.getConstant(1, VT); // X <= MAX --> true
1598 
1599  // Canonicalize setgt X, Min --> setne X, Min
1600  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1601  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1602  // Canonicalize setlt X, Max --> setne X, Max
1603  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1604  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1605 
1606  // If we have setult X, 1, turn it into seteq X, 0
1607  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1608  return DAG.getSetCC(dl, VT, N0,
1609  DAG.getConstant(MinVal, N0.getValueType()),
1610  ISD::SETEQ);
1611  // If we have setugt X, Max-1, turn it into seteq X, Max
1612  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1613  return DAG.getSetCC(dl, VT, N0,
1614  DAG.getConstant(MaxVal, N0.getValueType()),
1615  ISD::SETEQ);
1616 
1617  // If we have "setcc X, C0", check to see if we can shrink the immediate
1618  // by changing cc.
1619 
1620  // SETUGT X, SINTMAX -> SETLT X, 0
1621  if (Cond == ISD::SETUGT &&
1622  C1 == APInt::getSignedMaxValue(OperandBitSize))
1623  return DAG.getSetCC(dl, VT, N0,
1624  DAG.getConstant(0, N1.getValueType()),
1625  ISD::SETLT);
1626 
1627  // SETULT X, SINTMIN -> SETGT X, -1
1628  if (Cond == ISD::SETULT &&
1629  C1 == APInt::getSignedMinValue(OperandBitSize)) {
1630  SDValue ConstMinusOne =
1631  DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1632  N1.getValueType());
1633  return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1634  }
1635 
1636  // Fold bit comparisons when we can.
1637  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1638  (VT == N0.getValueType() ||
1639  (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1640  N0.getOpcode() == ISD::AND)
1641  if (ConstantSDNode *AndRHS =
1642  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1643  EVT ShiftTy = DCI.isBeforeLegalize() ?
1645  if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1646  // Perform the xform if the AND RHS is a single bit.
1647  if (AndRHS->getAPIntValue().isPowerOf2()) {
1648  return DAG.getNode(ISD::TRUNCATE, dl, VT,
1649  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1650  DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1651  }
1652  } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1653  // (X & 8) == 8 --> (X & 8) >> 3
1654  // Perform the xform if C1 is a single bit.
1655  if (C1.isPowerOf2()) {
1656  return DAG.getNode(ISD::TRUNCATE, dl, VT,
1657  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1658  DAG.getConstant(C1.logBase2(), ShiftTy)));
1659  }
1660  }
1661  }
1662 
1663  if (C1.getMinSignedBits() <= 64 &&
1664  !isLegalICmpImmediate(C1.getSExtValue())) {
1665  // (X & -256) == 256 -> (X >> 8) == 1
1666  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1667  N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1668  if (ConstantSDNode *AndRHS =
1669  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1670  const APInt &AndRHSC = AndRHS->getAPIntValue();
1671  if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1672  unsigned ShiftBits = AndRHSC.countTrailingZeros();
1673  EVT ShiftTy = DCI.isBeforeLegalize() ?
1675  EVT CmpTy = N0.getValueType();
1676  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1677  DAG.getConstant(ShiftBits, ShiftTy));
1678  SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
1679  return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1680  }
1681  }
1682  } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1683  Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1684  bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1685  // X < 0x100000000 -> (X >> 32) < 1
1686  // X >= 0x100000000 -> (X >> 32) >= 1
1687  // X <= 0x0ffffffff -> (X >> 32) < 1
1688  // X > 0x0ffffffff -> (X >> 32) >= 1
1689  unsigned ShiftBits;
1690  APInt NewC = C1;
1691  ISD::CondCode NewCond = Cond;
1692  if (AdjOne) {
1693  ShiftBits = C1.countTrailingOnes();
1694  NewC = NewC + 1;
1695  NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1696  } else {
1697  ShiftBits = C1.countTrailingZeros();
1698  }
1699  NewC = NewC.lshr(ShiftBits);
1700  if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
1701  EVT ShiftTy = DCI.isBeforeLegalize() ?
1703  EVT CmpTy = N0.getValueType();
1704  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1705  DAG.getConstant(ShiftBits, ShiftTy));
1706  SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
1707  return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1708  }
1709  }
1710  }
1711  }
1712 
1713  if (isa<ConstantFPSDNode>(N0.getNode())) {
1714  // Constant fold or commute setcc.
1715  SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1716  if (O.getNode()) return O;
1717  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1718  // If the RHS of an FP comparison is a constant, simplify it away in
1719  // some cases.
1720  if (CFP->getValueAPF().isNaN()) {
1721  // If an operand is known to be a nan, we can fold it.
1722  switch (ISD::getUnorderedFlavor(Cond)) {
1723  default: llvm_unreachable("Unknown flavor!");
1724  case 0: // Known false.
1725  return DAG.getConstant(0, VT);
1726  case 1: // Known true.
1727  return DAG.getConstant(1, VT);
1728  case 2: // Undefined.
1729  return DAG.getUNDEF(VT);
1730  }
1731  }
1732 
1733  // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1734  // constant if knowing that the operand is non-nan is enough. We prefer to
1735  // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1736  // materialize 0.0.
1737  if (Cond == ISD::SETO || Cond == ISD::SETUO)
1738  return DAG.getSetCC(dl, VT, N0, N0, Cond);
1739 
1740  // If the condition is not legal, see if we can find an equivalent one
1741  // which is legal.
1742  if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1743  // If the comparison was an awkward floating-point == or != and one of
1744  // the comparison operands is infinity or negative infinity, convert the
1745  // condition to a less-awkward <= or >=.
1746  if (CFP->getValueAPF().isInfinity()) {
1747  if (CFP->getValueAPF().isNegative()) {
1748  if (Cond == ISD::SETOEQ &&
1749  isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1750  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1751  if (Cond == ISD::SETUEQ &&
1752  isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1753  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1754  if (Cond == ISD::SETUNE &&
1755  isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1756  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1757  if (Cond == ISD::SETONE &&
1758  isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1759  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1760  } else {
1761  if (Cond == ISD::SETOEQ &&
1762  isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1763  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1764  if (Cond == ISD::SETUEQ &&
1765  isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1766  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1767  if (Cond == ISD::SETUNE &&
1768  isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1769  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1770  if (Cond == ISD::SETONE &&
1771  isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1772  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1773  }
1774  }
1775  }
1776  }
1777 
1778  if (N0 == N1) {
1779  // The sext(setcc()) => setcc() optimization relies on the appropriate
1780  // constant being emitted.
1781  uint64_t EqVal = 0;
1782  switch (getBooleanContents(N0.getValueType())) {
1785  EqVal = ISD::isTrueWhenEqual(Cond);
1786  break;
1788  EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1789  break;
1790  }
1791 
1792  // We can always fold X == X for integer setcc's.
1793  if (N0.getValueType().isInteger()) {
1794  return DAG.getConstant(EqVal, VT);
1795  }
1796  unsigned UOF = ISD::getUnorderedFlavor(Cond);
1797  if (UOF == 2) // FP operators that are undefined on NaNs.
1798  return DAG.getConstant(EqVal, VT);
1799  if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1800  return DAG.getConstant(EqVal, VT);
1801  // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1802  // if it is not already.
1803  ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1804  if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1805  getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1806  return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1807  }
1808 
1809  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1810  N0.getValueType().isInteger()) {
1811  if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1812  N0.getOpcode() == ISD::XOR) {
1813  // Simplify (X+Y) == (X+Z) --> Y == Z
1814  if (N0.getOpcode() == N1.getOpcode()) {
1815  if (N0.getOperand(0) == N1.getOperand(0))
1816  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1817  if (N0.getOperand(1) == N1.getOperand(1))
1818  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1819  if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1820  // If X op Y == Y op X, try other combinations.
1821  if (N0.getOperand(0) == N1.getOperand(1))
1822  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1823  Cond);
1824  if (N0.getOperand(1) == N1.getOperand(0))
1825  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1826  Cond);
1827  }
1828  }
1829 
1830  // If RHS is a legal immediate value for a compare instruction, we need
1831  // to be careful about increasing register pressure needlessly.
1832  bool LegalRHSImm = false;
1833 
1834  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1835  if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1836  // Turn (X+C1) == C2 --> X == C2-C1
1837  if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1838  return DAG.getSetCC(dl, VT, N0.getOperand(0),
1839  DAG.getConstant(RHSC->getAPIntValue()-
1840  LHSR->getAPIntValue(),
1841  N0.getValueType()), Cond);
1842  }
1843 
1844  // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1845  if (N0.getOpcode() == ISD::XOR)
1846  // If we know that all of the inverted bits are zero, don't bother
1847  // performing the inversion.
1848  if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1849  return
1850  DAG.getSetCC(dl, VT, N0.getOperand(0),
1851  DAG.getConstant(LHSR->getAPIntValue() ^
1852  RHSC->getAPIntValue(),
1853  N0.getValueType()),
1854  Cond);
1855  }
1856 
1857  // Turn (C1-X) == C2 --> X == C1-C2
1858  if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1859  if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1860  return
1861  DAG.getSetCC(dl, VT, N0.getOperand(1),
1862  DAG.getConstant(SUBC->getAPIntValue() -
1863  RHSC->getAPIntValue(),
1864  N0.getValueType()),
1865  Cond);
1866  }
1867  }
1868 
1869  // Could RHSC fold directly into a compare?
1870  if (RHSC->getValueType(0).getSizeInBits() <= 64)
1871  LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1872  }
1873 
1874  // Simplify (X+Z) == X --> Z == 0
1875  // Don't do this if X is an immediate that can fold into a cmp
1876  // instruction and X+Z has other uses. It could be an induction variable
1877  // chain, and the transform would increase register pressure.
1878  if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1879  if (N0.getOperand(0) == N1)
1880  return DAG.getSetCC(dl, VT, N0.getOperand(1),
1881  DAG.getConstant(0, N0.getValueType()), Cond);
1882  if (N0.getOperand(1) == N1) {
1883  if (DAG.isCommutativeBinOp(N0.getOpcode()))
1884  return DAG.getSetCC(dl, VT, N0.getOperand(0),
1885  DAG.getConstant(0, N0.getValueType()), Cond);
1886  if (N0.getNode()->hasOneUse()) {
1887  assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1888  // (Z-X) == X --> Z == X<<1
1889  SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1890  DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
1891  if (!DCI.isCalledByLegalizer())
1892  DCI.AddToWorklist(SH.getNode());
1893  return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1894  }
1895  }
1896  }
1897  }
1898 
1899  if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1900  N1.getOpcode() == ISD::XOR) {
1901  // Simplify X == (X+Z) --> Z == 0
1902  if (N1.getOperand(0) == N0)
1903  return DAG.getSetCC(dl, VT, N1.getOperand(1),
1904  DAG.getConstant(0, N1.getValueType()), Cond);
1905  if (N1.getOperand(1) == N0) {
1906  if (DAG.isCommutativeBinOp(N1.getOpcode()))
1907  return DAG.getSetCC(dl, VT, N1.getOperand(0),
1908  DAG.getConstant(0, N1.getValueType()), Cond);
1909  if (N1.getNode()->hasOneUse()) {
1910  assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1911  // X == (Z-X) --> X<<1 == Z
1912  SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1913  DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1914  if (!DCI.isCalledByLegalizer())
1915  DCI.AddToWorklist(SH.getNode());
1916  return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1917  }
1918  }
1919  }
1920 
1921  // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1922  // Note that where y is variable and is known to have at most
1923  // one bit set (for example, if it is z&1) we cannot do this;
1924  // the expressions are not equivalent when y==0.
1925  if (N0.getOpcode() == ISD::AND)
1926  if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1927  if (ValueHasExactlyOneBitSet(N1, DAG)) {
1928  Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1929  if (DCI.isBeforeLegalizeOps() ||
1930  isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1931  SDValue Zero = DAG.getConstant(0, N1.getValueType());
1932  return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1933  }
1934  }
1935  }
1936  if (N1.getOpcode() == ISD::AND)
1937  if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1938  if (ValueHasExactlyOneBitSet(N0, DAG)) {
1939  Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1940  if (DCI.isBeforeLegalizeOps() ||
1941  isCondCodeLegal(Cond, N1.getSimpleValueType())) {
1942  SDValue Zero = DAG.getConstant(0, N0.getValueType());
1943  return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1944  }
1945  }
1946  }
1947  }
1948 
1949  // Fold away ALL boolean setcc's.
1950  SDValue Temp;
1951  if (N0.getValueType() == MVT::i1 && foldBooleans) {
1952  switch (Cond) {
1953  default: llvm_unreachable("Unknown integer setcc!");
1954  case ISD::SETEQ: // X == Y -> ~(X^Y)
1955  Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1956  N0 = DAG.getNOT(dl, Temp, MVT::i1);
1957  if (!DCI.isCalledByLegalizer())
1958  DCI.AddToWorklist(Temp.getNode());
1959  break;
1960  case ISD::SETNE: // X != Y --> (X^Y)
1961  N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1962  break;
1963  case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1964  case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1965  Temp = DAG.getNOT(dl, N0, MVT::i1);
1966  N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1967  if (!DCI.isCalledByLegalizer())
1968  DCI.AddToWorklist(Temp.getNode());
1969  break;
1970  case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1971  case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1972  Temp = DAG.getNOT(dl, N1, MVT::i1);
1973  N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1974  if (!DCI.isCalledByLegalizer())
1975  DCI.AddToWorklist(Temp.getNode());
1976  break;
1977  case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1978  case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1979  Temp = DAG.getNOT(dl, N0, MVT::i1);
1980  N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1981  if (!DCI.isCalledByLegalizer())
1982  DCI.AddToWorklist(Temp.getNode());
1983  break;
1984  case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1985  case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1986  Temp = DAG.getNOT(dl, N1, MVT::i1);
1987  N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1988  break;
1989  }
1990  if (VT != MVT::i1) {
1991  if (!DCI.isCalledByLegalizer())
1992  DCI.AddToWorklist(N0.getNode());
1993  // FIXME: If running after legalize, we probably can't do this.
1994  N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1995  }
1996  return N0;
1997  }
1998 
1999  // Could not fold it.
2000  return SDValue();
2001 }
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned Log2_32_Ceil(uint32_t Value)
Definition: MathExtras.h:465
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:448
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT)
bool hasOneUse() const
bool hasOneUse() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:526
bool isUnindexed() const
isUnindexed - Return true if this is NOT a pre/post inc/dec load/store.
virtual bool isLegalICmpImmediate(int64_t) const
unsigned getValueSizeInBits() const
const SDValue & getOperand(unsigned Num) const
static bool isCommutativeBinOp(unsigned Opcode)
bool isTrueWhenEqual(CondCode Cond)
Definition: ISDOpcodes.h:809
const SDValue & getBasePtr() const
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:421
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
Definition: ValueTypes.h:190
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
EVT getShiftAmountTy(EVT LHSTy) const
bool isLittleEndian() const
bool isRound() const
isRound - Return true if the size is a power-of-two number of bytes.
Definition: ValueTypes.h:166
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const
MachinePointerInfo getWithOffset(int64_t O) const
virtual MVT getPointerTy(uint32_t=0) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
EVT getMemoryVT() const
getMemoryVT - Return the type of the in-memory value.
bool isSignedIntSetCC(CondCode Code)
Definition: ISDOpcodes.h:796
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
Definition: ValueTypes.h:196
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
SDNode * getNode() const
get the SDNode which holds the desired result
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1314
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
const DataLayout * getDataLayout() const
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned getOpcode() const
unsigned getUnorderedFlavor(CondCode Cond)
Definition: ISDOpcodes.h:817
CondCode getSetCCSwappedOperands(CondCode Operation)
bool isVolatile() const
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
const MachinePointerInfo & getPointerInfo() const
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
Definition: ValueTypes.h:178
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.cpp:737
SDValue getNOT(SDLoc DL, SDValue Val, EVT VT)
getNOT - Create a bitwise NOT operation as (XOR Val, -1).
const SDValue & getChain() const
static APInt getMinValue(unsigned numBits)
Gets minimum unsigned value of APInt for a specific bit width.
Definition: APInt.h:428
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
unsigned Log2_32(uint32_t Value)
Definition: MathExtras.h:452
ISD::LoadExtType getExtensionType() const
Class for arbitrary precision integers.
Definition: APInt.h:75
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
static APInt getMaxValue(unsigned numBits)
Gets maximum unsigned value of APInt for specific bit width.
Definition: APInt.h:416
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1865
uint64_t MinAlign(uint64_t A, uint64_t B)
Definition: MathExtras.h:544
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
unsigned countTrailingOnes() const
Count the number of trailing one bits.
Definition: APInt.h:1378
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, SDLoc dl)
FoldSetCC - Constant fold a setcc to true or false.
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Definition: APInt.h:431
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Definition: SelectionDAG.h:690
BooleanContent
Enum that describes how the target represents true/false values.
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
unsigned getAlignment() const
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
MVT getSimpleVT() const
Definition: ValueTypes.h:204
void TargetLowering::softenSetCCOperands ( SelectionDAG DAG,
EVT  VT,
SDValue NewLHS,
SDValue NewRHS,
ISD::CondCode CCCode,
SDLoc  dl 
) const
inherited

SoftenSetCCOperands - Soften the operands of a comparison. This code is shared among BR_CC, SELECT_CC, and SETCC handlers.

Definition at line 117 of file TargetLowering.cpp.

120  {
121  assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
122  && "Unsupported setcc type!");
123 
124  // Expand into one or more soft-fp libcall(s).
126  switch (CCCode) {
127  case ISD::SETEQ:
128  case ISD::SETOEQ:
129  LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
131  break;
132  case ISD::SETNE:
133  case ISD::SETUNE:
134  LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
136  break;
137  case ISD::SETGE:
138  case ISD::SETOGE:
139  LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
141  break;
142  case ISD::SETLT:
143  case ISD::SETOLT:
144  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
146  break;
147  case ISD::SETLE:
148  case ISD::SETOLE:
149  LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
151  break;
152  case ISD::SETGT:
153  case ISD::SETOGT:
154  LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
156  break;
157  case ISD::SETUO:
158  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
160  break;
161  case ISD::SETO:
162  LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
163  (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
164  break;
165  default:
166  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
168  switch (CCCode) {
169  case ISD::SETONE:
170  // SETONE = SETOLT | SETOGT
171  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
173  // Fallthrough
174  case ISD::SETUGT:
175  LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
177  break;
178  case ISD::SETUGE:
179  LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
181  break;
182  case ISD::SETULT:
183  LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
185  break;
186  case ISD::SETULE:
187  LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
189  break;
190  case ISD::SETUEQ:
191  LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
193  break;
194  default: llvm_unreachable("Do not know how to soften this setcc!");
195  }
196  }
197 
198  // Use the target specific return value for comparions lib calls.
199  EVT RetVT = getCmpLibcallReturnType();
200  SDValue Ops[2] = { NewLHS, NewRHS };
201  NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
202  dl).first;
203  NewRHS = DAG.getConstant(0, RetVT);
204  CCCode = getCmpLibcallCC(LC1);
205  if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
206  SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
207  getSetCCResultType(*DAG.getContext(), RetVT),
208  NewLHS, NewRHS, DAG.getCondCode(CCCode));
209  NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
210  dl).first;
211  NewLHS = DAG.getNode(ISD::SETCC, dl,
212  getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
213  NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
214  NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
215  NewRHS = SDValue();
216  }
217 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const
assert(Globals.size() > 1)
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
EVT getValueType() const
SDValue getCondCode(ISD::CondCode Cond)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
int ARMTargetLowering::StoreByValRegs ( CCState CCInfo,
SelectionDAG DAG,
SDLoc  dl,
SDValue Chain,
const Value OrigArg,
unsigned  InRegsParamRecordIdx,
unsigned  OffsetFromOrigArg,
unsigned  ArgOffset,
unsigned  ArgSize,
bool  ForceMutable,
unsigned  ByValStoreOffset,
unsigned  TotalArgRegsSaveSize 
) const
private

Definition at line 2788 of file ARMISelLowering.cpp.

2797  {
2798 
2799  // Currently, two use-cases possible:
2800  // Case #1. Non-var-args function, and we meet first byval parameter.
2801  // Setup first unallocated register as first byval register;
2802  // eat all remained registers
2803  // (these two actions are performed by HandleByVal method).
2804  // Then, here, we initialize stack frame with
2805  // "store-reg" instructions.
2806  // Case #2. Var-args function, that doesn't contain byval parameters.
2807  // The same: eat all remained unallocated registers,
2808  // initialize stack frame.
2809 
2810  MachineFunction &MF = DAG.getMachineFunction();
2811  MachineFrameInfo *MFI = MF.getFrameInfo();
2813  unsigned firstRegToSaveIndex, lastRegToSaveIndex;
2814  unsigned RBegin, REnd;
2815  if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2816  CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2817  firstRegToSaveIndex = RBegin - ARM::R0;
2818  lastRegToSaveIndex = REnd - ARM::R0;
2819  } else {
2820  firstRegToSaveIndex = CCInfo.getFirstUnallocated
2822  lastRegToSaveIndex = 4;
2823  }
2824 
2825  unsigned ArgRegsSize, ArgRegsSaveSize;
2826  computeRegArea(CCInfo, MF, InRegsParamRecordIdx, ArgSize,
2827  ArgRegsSize, ArgRegsSaveSize);
2828 
2829  // Store any by-val regs to their spots on the stack so that they may be
2830  // loaded by deferencing the result of formal parameter pointer or va_next.
2831  // Note: once stack area for byval/varargs registers
2832  // was initialized, it can't be initialized again.
2833  if (ArgRegsSaveSize) {
2834  unsigned Padding = ArgRegsSaveSize - ArgRegsSize;
2835 
2836  if (Padding) {
2837  assert(AFI->getStoredByValParamsPadding() == 0 &&
2838  "The only parameter may be padded.");
2839  AFI->setStoredByValParamsPadding(Padding);
2840  }
2841 
2842  int FrameIndex = MFI->CreateFixedObject(ArgRegsSaveSize,
2843  Padding +
2844  ByValStoreOffset -
2845  (int64_t)TotalArgRegsSaveSize,
2846  false);
2847  SDValue FIN = DAG.getFrameIndex(FrameIndex, getPointerTy());
2848  if (Padding) {
2849  MFI->CreateFixedObject(Padding,
2850  ArgOffset + ByValStoreOffset -
2851  (int64_t)ArgRegsSaveSize,
2852  false);
2853  }
2854 
2855  SmallVector<SDValue, 4> MemOps;
2856  for (unsigned i = 0; firstRegToSaveIndex < lastRegToSaveIndex;
2857  ++firstRegToSaveIndex, ++i) {
2858  const TargetRegisterClass *RC;
2859  if (AFI->isThumb1OnlyFunction())
2860  RC = &ARM::tGPRRegClass;
2861  else
2862  RC = &ARM::GPRRegClass;
2863 
2864  unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2865  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2866  SDValue Store =
2867  DAG.getStore(Val.getValue(1), dl, Val, FIN,
2868  MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i),
2869  false, false, 0);
2870  MemOps.push_back(Store);
2871  FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2872  DAG.getConstant(4, getPointerTy()));
2873  }
2874 
2875  AFI->setArgRegsSaveSize(ArgRegsSaveSize + AFI->getArgRegsSaveSize());
2876 
2877  if (!MemOps.empty())
2878  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2879  return FrameIndex;
2880  } else {
2881  if (ArgSize == 0) {
2882  // We cannot allocate a zero-byte object for the first variadic argument,
2883  // so just make up a size.
2884  ArgSize = 4;
2885  }
2886  // This will point to the next argument passed via stack.
2887  return MFI->CreateFixedObject(
2888  ArgSize, ArgOffset, !ForceMutable);
2889  }
2890 }
SDValue getValue(unsigned R) const
void getInRegsParamInfo(unsigned InRegsParamRecordIndex, unsigned &BeginReg, unsigned &EndReg) const
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
unsigned getInRegsParamsCount() const
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Abstract Stack Frame Information.
virtual MVT getPointerTy(uint32_t=0) const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const
unsigned getStoredByValParamsPadding() const
static const MCPhysReg GPRArgRegs[]
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
void computeRegArea(CCState &CCInfo, MachineFunction &MF, unsigned InRegsParamRecordIdx, unsigned ArgSize, unsigned &ArgRegsSize, unsigned &ArgRegsSaveSize) const
MachineFrameInfo * getFrameInfo()
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
void setStoredByValParamsPadding(unsigned p)
void setArgRegsSaveSize(unsigned s)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
unsigned getArgRegsSaveSize(unsigned Align=0) const
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
bool llvm::TargetLoweringBase::supportJumpTables ( ) const
inlineinherited

Return whether the target can generate code for jump tables.

Definition at line 827 of file TargetLowering.h.

827  {
828  return SupportJumpTables;
829  }
bool llvm::TargetLoweringBase::usesUnderscoreLongJmp ( ) const
inlineinherited

Determine if we should use _longjmp or longjmp to implement llvm.longjmp.

Definition at line 822 of file TargetLowering.h.

822  {
823  return UseUnderscoreLongJmp;
824  }
bool llvm::TargetLoweringBase::usesUnderscoreSetJmp ( ) const
inlineinherited

Determine if we should use _setjmp or setjmp to implement llvm.setjmp.

Definition at line 817 of file TargetLowering.h.

817  {
818  return UseUnderscoreSetJmp;
819  }
void ARMTargetLowering::VarArgStyleRegisters ( CCState CCInfo,
SelectionDAG DAG,
SDLoc  dl,
SDValue Chain,
unsigned  ArgOffset,
unsigned  TotalArgRegsSaveSize,
bool  ForceMutable = false 
) const
private

Definition at line 2894 of file ARMISelLowering.cpp.

2898  {
2899  MachineFunction &MF = DAG.getMachineFunction();
2901 
2902  // Try to store any remaining integer argument regs
2903  // to their spots on the stack so that they may be loaded by deferencing
2904  // the result of va_next.
2905  // If there is no regs to be stored, just point address after last
2906  // argument passed via stack.
2907  int FrameIndex =
2908  StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
2909  CCInfo.getInRegsParamsCount(), 0, ArgOffset, 0, ForceMutable,
2910  0, TotalArgRegsSaveSize);
2911 
2912  AFI->setVarArgsFrameIndex(FrameIndex);
2913 }
int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, const Value *OrigArg, unsigned InRegsParamRecordIdx, unsigned OffsetFromOrigArg, unsigned ArgOffset, unsigned ArgSize, bool ForceMutable, unsigned ByValStoreOffset, unsigned TotalArgRegsSaveSize) const
unsigned getInRegsParamsCount() const
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
void setVarArgsFrameIndex(int Index)
bool TargetLowering::verifyReturnAddressArgumentIsConstant ( SDValue  Op,
SelectionDAG DAG 
) const
inherited

Definition at line 2772 of file TargetLowering.cpp.

2772  {
2773  if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2774  DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2775  "be a constant integer");
2776  return true;
2777  }
2778 
2779  return false;
2780 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
void emitError(unsigned LocCookie, const Twine &ErrorStr)
const SDValue & getOperand(unsigned i) const

Field Documentation

unsigned llvm::ARMTargetLowering::ARMPCLabelIndex
private

ARMPCLabelIndex - Keep track of the number of ARM PC labels created.

Definition at line 416 of file ARMISelLowering.h.

const InstrItineraryData* llvm::ARMTargetLowering::Itins
private

Definition at line 412 of file ARMISelLowering.h.

bool llvm::TargetLoweringBase::MaskAndBranchFoldingIsLegal
protectedinherited

MaskAndBranchFoldingIsLegal - Indicates if the target supports folding a mask of a single bit, a compare, and a branch into a single instruction.

Definition at line 1842 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpy
protectedinherited

Specify maximum bytes of store instructions per memcpy call.

When lowering @llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.

Definition at line 1814 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
protectedinherited

Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute.

Definition at line 1818 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmove
protectedinherited

Specify maximum bytes of store instructions per memmove call.

When lowering @llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.

Definition at line 1830 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
protectedinherited

Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute.

Definition at line 1834 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemset
protectedinherited

Specify maximum number of store instructions per memset call.

When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.

Definition at line 1797 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
protectedinherited

Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.

Definition at line 1801 of file TargetLowering.h.

bool llvm::TargetLoweringBase::PredictableSelectIsExpensive
protectedinherited

Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.

Definition at line 1838 of file TargetLowering.h.

const TargetRegisterInfo* llvm::ARMTargetLowering::RegInfo
private

Definition at line 410 of file ARMISelLowering.h.

const ARMSubtarget* llvm::ARMTargetLowering::Subtarget
private

Subtarget - Keep a pointer to the ARMSubtarget around so that we can make the right decision when generating code for different targets.

Definition at line 408 of file ARMISelLowering.h.


The documentation for this class was generated from the following files: